RISC-V processor model
☆11Nov 10, 2020Updated 5 years ago
Alternatives and similar repositories for riscv
Users that are interested in riscv are comparing it to the libraries listed below
Sorting:
- An implementation of a BinaryConnect network for cifar10☆11Nov 4, 2019Updated 6 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Aug 14, 2015Updated 10 years ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆17Sep 17, 2013Updated 12 years ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- Some design patterns implements in C++.☆10Aug 14, 2024Updated last year
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- ☆10Jun 21, 2022Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Solving the inverse kinematics problem of a 3 Link Planar Manipulator using neural networks.☆10Jul 19, 2020Updated 5 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …☆42Jun 2, 2023Updated 2 years ago
- ☆13Mar 4, 2017Updated 8 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- The Risk Modeller’s Toolkit prototype code.☆11May 7, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Dec 7, 2025Updated 2 months ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- ☆11May 8, 2022Updated 3 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- A fast implementation of mmap in Python☆14Jun 3, 2020Updated 5 years ago
- ☆12Nov 8, 2023Updated 2 years ago
- National Seismic Hazard Mapping Project (NSHMP) Web Service Code☆10Dec 8, 2022Updated 3 years ago
- Porting SMBUS/PMBUS Stack Middleware for STM32F407 MCU☆11Jul 5, 2018Updated 7 years ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- SoCRocket - Core Repository☆38Mar 6, 2017Updated 8 years ago
- Contributions to the wiki☆13Sep 18, 2012Updated 13 years ago
- Design of the site for Ukrainian OSM Community☆10Dec 10, 2024Updated last year