ArchC / riscv
RISC-V processor model
☆10Updated 4 years ago
Alternatives and similar repositories for riscv:
Users that are interested in riscv are comparing it to the libraries listed below
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated 2 weeks ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆16Updated 11 years ago
- SystemVerilog Logger☆17Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- Advanced Debug Interface☆14Updated 2 months ago
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆12Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆17Updated 6 years ago
- Network on Chip for MPSoC☆26Updated 2 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Updated 9 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆24Updated 2 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆33Updated last year
- SoCRocket - Core Repository☆35Updated 8 years ago
- A configurable general purpose graphics processing unit for☆11Updated 5 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- Simple single-port AXI memory interface☆40Updated 9 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- PCI Express controller model☆53Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆22Updated 6 years ago