☆31Aug 8, 2020Updated 5 years ago
Alternatives and similar repositories for basic_cache_core
Users that are interested in basic_cache_core are comparing it to the libraries listed below
Sorting:
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- A Verilog implementation of a processor cache.☆36Dec 29, 2017Updated 8 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 11 years ago
- Design and UVM-TB of RISC -V Microprocessor☆33Jun 27, 2024Updated last year
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Jun 19, 2020Updated 5 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- ☆17Dec 21, 2020Updated 5 years ago
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- systemc建模相关☆28Jun 11, 2014Updated 11 years ago
- Two Level Cache Controller implementation in Verilog HDL☆57Jul 9, 2020Updated 5 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆26Mar 26, 2020Updated 5 years ago
- vector accelerating unit☆35Dec 1, 2020Updated 5 years ago
- 21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 sin…☆14Apr 11, 2023Updated 2 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- An AXI DDR3 SDRAM controller for FPGA☆44Dec 30, 2023Updated 2 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆16Jul 1, 2024Updated last year
- ☆15Feb 5, 2026Updated 3 weeks ago