Alternatives and similar repositories for basic_cache_core

Users that are interested in basic_cache_core are comparing it to the libraries listed below

• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆53Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / fpu
  ☆51Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆41Updated 2 years ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated last month
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆34Updated 2 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆58Updated last week
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 5 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆74Updated 7 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆56Updated 2 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆65Updated 5 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆25Updated 8 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆76Updated 10 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆13Updated 2 years ago