Alternatives and similar repositories for sargantana:

Users that are interested in sargantana are comparing it to the libraries listed below

• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆99Updated this week
• chipsalliance / uvm-verilator
  ☆88Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆80Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆139Updated 2 weeks ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆129Updated last week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 5 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 6 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆87Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆182Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆149Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆158Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 5 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆111Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated 2 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆169Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆79Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆181Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆132Updated 5 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆85Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆80Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆81Updated 5 months ago