bsc-loca / sargantana
☆92Updated last year
Alternatives and similar repositories for sargantana:
Users that are interested in sargantana are comparing it to the libraries listed below
- A Fast, Low-Overhead On-chip Network☆201Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆92Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆149Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆96Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆80Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated 2 weeks ago
- RISC-V Nox core☆62Updated last month
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- Generic Register Interface (contains various adapters)☆117Updated 7 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- The multi-core cluster of a PULP system.☆91Updated last week
- Simple runtime for Pulp platforms☆47Updated last month
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- ☆173Updated last year
- SystemVerilog synthesis tool☆190Updated 2 months ago