bsc-loca / sargantana
☆86Updated 10 months ago
Alternatives and similar repositories for sargantana:
Users that are interested in sargantana are comparing it to the libraries listed below
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆74Updated 11 months ago
- Chisel RISC-V Vector 1.0 Implementation☆82Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆135Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated this week
- A SystemVerilog source file pickler.☆55Updated 4 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆61Updated 6 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆181Updated last week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- Unit tests generator for RVV 1.0☆77Updated last month
- Vector processor for RISC-V vector ISA☆115Updated 4 years ago
- Generic Register Interface (contains various adapters)☆110Updated 5 months ago
- ☆88Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆165Updated this week
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- SystemVerilog frontend for Yosys☆79Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- The multi-core cluster of a PULP system.☆80Updated last week
- pulp_soc is the core building component of PULP based SoCs☆79Updated this week
- RISC-V Formal Verification Framework☆128Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆100Updated last year
- RISC-V System on Chip Template☆156Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆158Updated 2 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month