smunaut / doom_riscv
Doom classic port to lightweight RISC‑V
☆91Updated 2 years ago
Alternatives and similar repositories for doom_riscv:
Users that are interested in doom_riscv are comparing it to the libraries listed below
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker☆98Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆91Updated 8 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 2 years ago
- CoreScore☆151Updated 3 months ago
- Exploring gate level simulation☆57Updated 2 weeks ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Virtual Development Board☆59Updated 3 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆98Updated last year
- Example LED blinking project for your FPGA dev board of choice☆175Updated 2 months ago
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆251Updated last year
- This repository contains small example designs that can be used with the open source icestorm flow.☆147Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆167Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆103Updated 9 months ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- FPGA GPU design for DE1-SoC☆73Updated 3 years ago
- USB Serial on the TinyFPGA BX☆136Updated 3 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated this week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- Nitro USB FPGA core☆84Updated last year
- ☆69Updated 8 months ago
- Miscellaneous ULX3S examples (advanced)☆77Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 3 months ago
- Board definitions for Amaranth HDL☆114Updated last month
- Minimal DVI / HDMI Framebuffer☆80Updated 4 years ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆173Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 6 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆81Updated this week
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago