Alternatives and similar repositories for beehive

Users that are interested in beehive are comparing it to the libraries listed below

• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆67Updated 7 months ago
• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆45Updated 2 years ago
• Xilinx / AlveoLink
  This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…
  ☆21Updated 2 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• CESNET / ndk-fpga
  Network Development Kit (NDK) for FPGA cards with example application
  ☆59Updated this week
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆108Updated this week
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆48Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆67Updated 9 months ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆118Updated 7 months ago
• rick-heig / zynq7-cosim
  ☆15Updated 5 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆86Updated 3 months ago
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆16Updated last year
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆26Updated 3 years ago
• Xilinx / pcie_qdma_ats_example
  ☆25Updated 4 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆48Updated last week
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆18Updated 5 years ago
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆23Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆52Updated 2 years ago
• Xilinx / HLS_packet_processing
  ☆47Updated 5 years ago
• NetFPGA / NetFPGA-PLUS
  ☆53Updated last year
• datenlord / blue-rdma
  RoCEv2 hardware implementation in Bluespec SystemVerilog
  ☆29Updated 10 months ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆44Updated 5 months ago
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆35Updated 4 years ago
• UCLA-VAST / HT-Deflate-FPGA
  ☆16Updated 3 years ago
• merledu / OpenTCAM
  An open-source Ternary Content Addressable Memory (TCAM) compiler.
  ☆29Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆60Updated 2 years ago
• ChenJianyunp / FPGA-Snappy-Decompressor
  A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
  ☆23Updated 2 years ago