beehive-fpga / beehive
☆14Updated 2 months ago
Alternatives and similar repositories for beehive:
Users that are interested in beehive are comparing it to the libraries listed below
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 3 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- Verilog PCI express components☆22Updated last year
- The official NaplesPU hardware code repository☆15Updated 5 years ago
- Framework for FPGA-accelerated Middlebox Development☆43Updated 2 years ago
- corundum work on vu13p☆18Updated last year
- ☆26Updated 2 weeks ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆28Updated 9 months ago
- ☆14Updated 2 months ago
- ☆14Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆23Updated 7 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- PCI Express controller model☆55Updated 2 years ago
- Ethernet switch implementation written in Verilog☆46Updated last year
- DUTH RISC-V Microprocessor☆18Updated 4 months ago
- ☆21Updated last week
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆48Updated last year
- ☆23Updated 3 years ago
- ☆13Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆34Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 5 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆25Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆44Updated this week