Alternatives and similar repositories for beehive

Users that are interested in beehive are comparing it to the libraries listed below

• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆44Updated 2 years ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆19Updated last year
• esnet / esnet-fpga-library
  ESnet general-purpose FPGA design library.
  ☆12Updated 2 weeks ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆24Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated 2 years ago
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆15Updated last year
• corundum / verilog-pcie
  Verilog PCI express components
  ☆22Updated last year
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 8 months ago
• UCLA-VAST / HT-Deflate-FPGA
  ☆14Updated 2 years ago
• NetFPGA / NetFPGA-PLUS
  ☆51Updated 10 months ago
• TsaiAnson / verif
  ☆12Updated 3 years ago
• merledu / OpenTCAM
  An open-source Ternary Content Addressable Memory (TCAM) compiler.
  ☆28Updated 9 months ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆17Updated 5 years ago
• Xilinx / pcie_qdma_ats_example
  ☆23Updated 4 years ago
• esa-tu-darmstadt / SCAIE-V-2.0
  ☆14Updated 3 months ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 2 months ago
• utnslab / RingleaderNIC
  ☆14Updated 2 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆37Updated last year
• chipsalliance / aib-protocols
  ☆25Updated last year
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆47Updated last year
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆20Updated 9 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆66Updated 4 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• datenlord / blue-rdma
  RoCEv2 hardware implementation in Bluespec SystemVerilog
  ☆24Updated 8 months ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆84Updated last week
• pulp-platform / axi_llc
  ☆27Updated last month
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆62Updated 6 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆16Updated 5 years ago