☆17Aug 14, 2025Updated 6 months ago
Alternatives and similar repositories for core_tile
Users that are interested in core_tile are comparing it to the libraries listed below
Sorting:
- QuickEd is a high-performance exact sequence alignment based on the bound-and-align paradigm.☆28May 5, 2025Updated 9 months ago
- ☆132Aug 14, 2025Updated 6 months ago
- HARV - HArdened Risc-V☆16Mar 10, 2022Updated 3 years ago
- A reliable, real-time subsystem for the Carfield SoC☆19Dec 2, 2025Updated 3 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- An energy-efficient RISC-V floating-point compute cluster.☆123Feb 21, 2026Updated last week
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆15Nov 11, 2025Updated 3 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37May 4, 2024Updated last year
- ☆19Feb 12, 2026Updated 2 weeks ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- Verification of an Asynchronous FIFO using UVM & SVA☆11Jun 26, 2025Updated 8 months ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- Library JPEG Quant Smooth☆12Aug 18, 2023Updated 2 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Benchmarking for multiple AWS S3 libraries.☆15Feb 3, 2026Updated 3 weeks ago
- Final year research project to design a programmable virtual switch based on the specifications of a TSN to be implemented on a TSN netwo…☆13Nov 17, 2020Updated 5 years ago
- The PCB design files for the Maslow4☆12Jun 24, 2025Updated 8 months ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆16Feb 12, 2026Updated 2 weeks ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 2 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- The official implement of paper S2-VER: Semi-Supervised Visual Emotion Recognition☆11Apr 28, 2024Updated last year
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆119Updated this week
- grpc messages over IPC or WebSockets using TypeScript☆11May 30, 2018Updated 7 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Mar 31, 2021Updated 4 years ago
- ☆11Dec 15, 2023Updated 2 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Jan 21, 2024Updated 2 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board☆11Jan 1, 2024Updated 2 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 4 months ago
- Vitis-AI 1.3 TensorFlow2 flow with a custom CNN model, targeted ZCU102 evaluation board.☆15Apr 6, 2021Updated 4 years ago
- ☆15Oct 20, 2025Updated 4 months ago
- ☆14Oct 7, 2020Updated 5 years ago
- ☆13Feb 10, 2026Updated 2 weeks ago
- Nix flake for more up-to-date versions of EDA tools☆20Feb 20, 2026Updated last week