☆18Jun 8, 2026Updated last month
Alternatives and similar repositories for core_tile
Users that are interested in core_tile are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆146Jun 8, 2026Updated last month
- This technology implements a PQC accelerator for FPGA-based SoCs using HLS. It supports CRYSTALS-Kyber (ML-KEM) and CRYSTALS-Dilithium (M…☆23Jul 16, 2025Updated last year
- A general technique to reduce memory consumption and improve the performance of gap-affine and dual gap-affine sequence alignment algorit…☆16Jan 22, 2026Updated 5 months ago
- A reliable, real-time subsystem for the Carfield SoC☆21Dec 2, 2025Updated 7 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆12May 29, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆18Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆138Updated this week
- ☆19Aug 27, 2022Updated 3 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- ☆15Nov 26, 2024Updated last year
- ☆17Apr 6, 2022Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated 2 years ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆18Updated this week
- Cohort Project☆19Oct 23, 2025Updated 8 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- HARV - HArdened Risc-V☆18Mar 10, 2022Updated 4 years ago
- The official repository of metro-mpi☆18Sep 3, 2025Updated 10 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆36Jul 2, 2026Updated 2 weeks ago
- ☆23Sep 17, 2024Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆64Jul 9, 2020Updated 6 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 9 months ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆30Jul 1, 2026Updated 3 weeks ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆45Feb 23, 2026Updated 4 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆18Jun 29, 2026Updated 3 weeks ago
- Example of an ELF parser to learn about the ELF format☆11Oct 6, 2024Updated last year
- The Qiskit Hackathon Barcelona is an immersive competition featuring live engagement, teamwork, and mentorship by expert researchers, dev…☆23Apr 10, 2023Updated 3 years ago
- Data Structures and Algorithms library with strong emphasis on functional programming☆18Updated this week
- Final year research project to design a programmable virtual switch based on the specifications of a TSN to be implemented on a TSN netwo…☆13Nov 17, 2020Updated 5 years ago
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 5 years ago
- ☆18May 1, 2020Updated 6 years ago
- ☆15Jan 19, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a fork of zsim (see https://github.com/s5z/zsim) which integrates the NVMain main memory simulator, adding 3D stacking and non-vo…☆26Jan 15, 2015Updated 11 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- ☆12Apr 19, 2022Updated 4 years ago
- The multi-core cluster of a PULP system.☆114Updated this week
- grpc messages over IPC or WebSockets using TypeScript☆11May 30, 2018Updated 8 years ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 3 years ago