bsc-loca / core_tileLinks
☆14Updated last week
Alternatives and similar repositories for core_tile
Users that are interested in core_tile are comparing it to the libraries listed below
Sorting:
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 3 weeks ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- A Fast, Low-Overhead On-chip Network☆220Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- Two Level Cache Controller implementation in Verilog HDL☆51Updated 5 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated 2 weeks ago
- ☆107Updated last week
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆11Updated last year
- A demo system for Ibex including debug support and some peripherals☆74Updated 2 months ago
- ☆97Updated last year
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 5 months ago
- RISC-V Nox core☆66Updated 3 weeks ago
- This is the fork of CVA6 intended for PULP development.☆21Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 8 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆108Updated last week
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- The OpenPiton Platform☆16Updated last year
- ☆30Updated 3 weeks ago
- Vector processor for RISC-V vector ISA☆125Updated 4 years ago
- Administrative repository for the Integrated Matrix Extension Task Group☆26Updated 2 weeks ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆205Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆128Updated 3 weeks ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated 3 weeks ago
- ☆15Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated last week
- ☆48Updated 4 months ago
- Self checking RISC-V directed tests☆111Updated 2 months ago