Stuart-Swan / Matchlib-Examples-Kit-For-Accellera-Synthesis-WGLinks
☆12Updated this week
Alternatives and similar repositories for Matchlib-Examples-Kit-For-Accellera-Synthesis-WG
Users that are interested in Matchlib-Examples-Kit-For-Accellera-Synthesis-WG are comparing it to the libraries listed below
Sorting:
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last month
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆125Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated 3 weeks ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated this week
- Example code for Modern SystemC using Modern C++☆69Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Project repo for the POSH on-chip network generator☆52Updated 9 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- ☆29Updated last year
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Updated last year
- ☆33Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- matrix-coprocessor for RISC-V☆26Updated 3 weeks ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆26Updated 3 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- ☆13Updated 3 years ago
- Advanced Architecture Labs with CVA6☆72Updated last year
- SoCRocket - Core Repository☆38Updated 8 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- DUTH RISC-V Microprocessor☆23Updated last year
- Administrative repository for the Integrated Matrix Extension Task Group☆30Updated 3 weeks ago
- Public release☆58Updated 6 years ago