vlsi-lab / len5Links
LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
☆17Updated last month
Alternatives and similar repositories for len5
Users that are interested in len5 are comparing it to the libraries listed below
Sorting:
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆39Updated 4 months ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆73Updated 4 years ago
- ☆110Updated 3 weeks ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Updated 3 weeks ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆34Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated 6 months ago
- ☆32Updated last week
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Platform Level Interrupt Controller☆44Updated last year
- ☆12Updated 4 years ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- ☆37Updated 6 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- DUTH RISC-V Microprocessor☆22Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆21Updated last year
- SystemVerilog modules and classes commonly used for verification☆51Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago