LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
☆21Oct 22, 2025Updated 5 months ago
Alternatives and similar repositories for len5
Users that are interested in len5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆14Nov 12, 2025Updated 4 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80May 22, 2024Updated last year
- ☆133Aug 14, 2025Updated 7 months ago
- ☆20May 13, 2025Updated 10 months ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆251Updated this week
- A C version of Branch Predictor Simulator☆17Jul 10, 2024Updated last year
- matrix-coprocessor for RISC-V☆31Feb 27, 2026Updated 3 weeks ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆39Updated this week
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- ☆21May 8, 2025Updated 10 months ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆80Jan 28, 2026Updated last month
- A C++ neural network library for machine learning☆15May 1, 2024Updated last year
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 3 years ago
- ☆18Jul 26, 2024Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆21Jul 7, 2024Updated last year
- C++ 17 Hardware abstraction layer generator from systemrdl☆14Mar 3, 2026Updated 3 weeks ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43May 5, 2023Updated 2 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆19Sep 14, 2023Updated 2 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- ☆14Jul 5, 2019Updated 6 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆15Oct 15, 2016Updated 9 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- The Repository contains the code of various Digital Circuits☆12Aug 7, 2023Updated 2 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆100Updated this week