vlsi-lab / len5Links
LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
☆16Updated last year
Alternatives and similar repositories for len5
Users that are interested in len5 are comparing it to the libraries listed below
Sorting:
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 7 months ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 11 months ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆14Updated this week
- ☆34Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- ☆12Updated 2 months ago
- ☆11Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 2 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆14Updated 4 months ago
- ☆30Updated 2 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- ☆14Updated 2 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆19Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆57Updated 2 years ago
- Platform Level Interrupt Controller☆41Updated last year
- ☆20Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆62Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 5 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- YosysHQ SVA AXI Properties☆40Updated 2 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆12Updated last year