vlsi-lab / len5
LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
☆16Updated 11 months ago
Alternatives and similar repositories for len5:
Users that are interested in len5 are comparing it to the libraries listed below
- CORE-V MCU UVM Environment and Test Bench☆21Updated 8 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- Xilinx AXI VIP example of use☆37Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆31Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- DUTH RISC-V Microprocessor☆18Updated 4 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- ☆12Updated 2 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆40Updated 3 years ago
- SoC Based on ARM Cortex-M3☆30Updated last week
- SystemVerilog modules and classes commonly used for verification☆47Updated 3 months ago
- ☆13Updated 2 years ago
- ☆26Updated 5 years ago
- ☆19Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- ☆21Updated 5 years ago
- ☆12Updated 2 weeks ago
- Platform Level Interrupt Controller☆39Updated 11 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- ☆28Updated last year
- ☆20Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago