Alternatives and similar repositories for cheriot-ibex:

Users that are interested in cheriot-ibex are comparing it to the libraries listed below

• lowRISC / sonata-system
  A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
  ☆37Updated last week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆81Updated last week
• chipsalliance / Cores-SweRV_fpga
  ☆41Updated 4 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆102Updated last month
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆139Updated 3 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆68Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 11 months ago
• olofk / corescore
  CoreScore
  ☆142Updated this week
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆69Updated 5 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆177Updated 6 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated 2 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆82Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆123Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆168Updated last month
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆59Updated last week
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆34Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆165Updated 6 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆77Updated 3 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆220Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆65Updated 9 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆259Updated this week
• riscv / riscv-aia
  ☆85Updated 2 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 9 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆127Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆204Updated 2 weeks ago