comsec-group / mucfiLinks
Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's operands to the program counter.
☆16Updated 5 months ago
Alternatives and similar repositories for mucfi
Users that are interested in mucfi are comparing it to the libraries listed below
Sorting:
- ☆26Updated 8 months ago
- A fork of Yosys that integrates the CellIFT pass☆13Updated 4 months ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆21Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 3 years ago
- Code repository for Coppelia tool☆23Updated 5 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated last week
- Testing processors with Random Instruction Generation☆50Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- ☆20Updated last year
- ☆16Updated 4 years ago
- RTLCheck☆23Updated 7 years ago
- The purpose of the repo is to support CORE-V Wally architectural verification☆15Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Hardware Formal Verification☆16Updated 5 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆23Updated 10 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Updated last month
- RISC-V IOMMU Demo (Linux & Bao)☆23Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 2 months ago
- Simple UVM environment for experimenting with Verilator.☆28Updated last month
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- IOPMP IP☆21Updated 5 months ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated last week
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆26Updated 2 years ago
- ☆19Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- RTLMeter benchmark suite☆28Updated this week
- ☆10Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago