comsec-group / mucfiLinks
Microarchitectural control flow integrity (πCFI) verification checks whether there exists a control or data flow from instruction's operands to the program counter.
β16Updated 7 months ago
Alternatives and similar repositories for mucfi
Users that are interested in mucfi are comparing it to the libraries listed below
Sorting:
- β27Updated 10 months ago
- A fork of Yosys that integrates the CellIFT passβ13Updated 6 months ago
- β20Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operatβ¦β22Updated last year
- Testing processors with Random Instruction Generationβ55Updated 3 weeks ago
- A Modular Open-Source Hardware Fuzzing Frameworkβ36Updated 4 years ago
- Code repository for Coppelia toolβ23Updated 5 years ago
- Hardware Formal Verificationβ17Updated 5 years ago
- The purpose of the repo is to support CORE-V Wally architectural verificationβ17Updated 2 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripheralsβ27Updated 2 years ago
- The RTL source for AnyCore RISC-Vβ33Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations madeβ¦β98Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocolβ37Updated last year
- β19Updated last year
- β17Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.β61Updated last month
- β10Updated 4 years ago
- All the tools you need to reproduce the CellIFT paper experimentsβ23Updated 11 months ago
- CocoAlma is an execution-aware tool for formal verification of masked implementationsβ24Updated last year
- YosysHQ SVA AXI Propertiesβ43Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.β28Updated 7 months ago
- IOPMP IPβ22Updated 6 months ago
- RISC-V IOMMU Demo (Linux & Bao)β24Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platformβ28Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1β20Updated 3 months ago
- Hardware Formal Verification Toolβ86Updated last week
- RTLMeter benchmark suiteβ29Updated 2 weeks ago
- Simple UVM environment for experimenting with Verilator.β28Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISAβ34Updated last month
- A DMA Controller for RISCV CPUsβ13Updated 10 years ago