Alternatives and similar repositories for mucfi

Users that are interested in mucfi are comparing it to the libraries listed below

• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆14Updated last week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 5 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• verilator / rtlmeter
  RTLMeter benchmark suite
  ☆23Updated 2 weeks ago
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• comsec-group / encarsia
  ☆21Updated 5 months ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆24Updated last week
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆21Updated 7 months ago
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆25Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 3 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated 11 months ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆40Updated 2 weeks ago
• kagandikmen / TPU.sv
  Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
  ☆18Updated 2 months ago
• ics-jku / spinalfuzz
  Fuzzing for SpinalHDL
  ☆16Updated 2 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated 2 weeks ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆37Updated 4 months ago
• efeslab / hardware-bugbase
  ☆18Updated last year
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆14Updated 10 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆88Updated last year
• antmicro / rowhammer-tester
  ☆64Updated 4 months ago
• sterin / super-prove-build
  ☆13Updated 5 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago