Alternatives and similar repositories for mucfi

Users that are interested in mucfi are comparing it to the libraries listed below

• comsec-group / encarsia
  ☆25Updated 7 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 5 months ago
• comsec-group / cellift-yosys
  A fork of Yosys that integrates the CellIFT pass
  ☆13Updated 4 months ago
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆15Updated last week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆21Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• verilator / rtlmeter
  RTLMeter benchmark suite
  ☆28Updated 3 weeks ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆28Updated 2 weeks ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆26Updated 2 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆48Updated last month
• iscas-tis / CHA
  ☆19Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• zhemao / riscv-dma
  A DMA Controller for RISCV CPUs
  ☆13Updated 10 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated 5 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆116Updated this week
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• sterin / super-prove-build
  ☆14Updated 5 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆92Updated last year
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆22Updated 9 months ago
• pulp-platform / ELAU
  ☆20Updated last year