comsec-group / mucfi
Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's operands to the program counter.
☆12Updated 2 months ago
Alternatives and similar repositories for mucfi:
Users that are interested in mucfi are comparing it to the libraries listed below
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 6 months ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Testing processors with Random Instruction Generation☆37Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆23Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated this week
- Hardware Formal Verification☆15Updated 4 years ago
- Fuzzing for SpinalHDL☆16Updated 2 years ago
- ☆19Updated 10 months ago
- ☆12Updated 8 months ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- Simple UVM environment for experimenting with Verilator.☆20Updated last week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated last week
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆13Updated 3 weeks ago
- ☆14Updated last month
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated this week
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- ☆16Updated 3 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- ☆18Updated 10 months ago