☆33Jan 7, 2025Updated last year
Alternatives and similar repositories for svase
Users that are interested in svase are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Jul 1, 2026Updated last month
- ☆65Mar 31, 2025Updated last year
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ☆63Jul 11, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆14Jun 12, 2024Updated 2 years ago
- ☆37Jul 23, 2026Updated 2 weeks ago
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- An automatic clock gating utility☆53Apr 15, 2025Updated last year
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆29Jan 6, 2026Updated 7 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11Aug 1, 2026Updated last week
- SystemVerilog design elaborator into word-level netlist form☆245Aug 3, 2026Updated last week
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆37Updated this week
- A pipelined RISC-V processor☆65Dec 1, 2023Updated 2 years ago
- CATCH 1.0, Initial full release of CATCH cost model.☆19Mar 3, 2026Updated 5 months ago
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆17Apr 3, 2025Updated last year
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 5 months ago
- A dependency management tool for hardware projects.☆383Updated this week
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Scalable Interface for RISC-V ISA Extensions☆26Jul 22, 2026Updated 2 weeks ago
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A configurable SRAM generator☆67Jun 28, 2026Updated last month
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 4 months ago
- Hardware transactions library for Amaranth☆30Updated this week
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆22Apr 1, 2025Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆91Updated this week
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 2 weeks ago
- Spire is a Python embedded domain-specific language (DSL) for RTL generation. Its built-in optimizations reduce area and delay of circuit…☆28Aug 3, 2026Updated last week
- A novel Design-for-Test flow using LibreLane☆45May 9, 2026Updated 3 months ago
- A Python package for creating and solving constrained randomization problems.☆19Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Efabless mpw7 submission☆16May 6, 2024Updated 2 years ago
- SystemVerilog compiler and language services☆1,105Updated this week
- ☆152Jun 16, 2026Updated last month
- Project template for wafer.space MPW runs using the gf180mcu PDK☆42Jul 21, 2026Updated 2 weeks ago
- A Python library for working with logic networks, synthesis, and optimization.☆88Updated this week
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 4 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆99May 8, 2026Updated 3 months ago