Alternatives and similar repositories for svase

Users that are interested in svase are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆137Updated last week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• snishizawa / libretto
  Characterizer
  ☆30Updated 2 weeks ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆57Updated 3 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆41Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆176Updated this week
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 5 years ago
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆31Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆67Updated last year
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆19Updated 4 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆40Updated last week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆94Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆76Updated 5 years ago
• iic-jku / IIC-RALF
  Reinforcement learning assisted analog layout design flow.
  ☆32Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year