TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)
☆53Jul 22, 2026Updated 3 months ago
Alternatives and similar repositories for TuRTLe
Users that are interested in TuRTLe are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augment…☆14Mar 24, 2025Updated last year
- ☆248Jun 8, 2026Updated 4 months ago
- ☆13Jun 8, 2026Updated 4 months ago
- LintLLM is an open-source Verilog linting framework powered by Large Language Models (LLMs).☆12Aug 14, 2026Updated 2 months ago
- ☆10Sep 29, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆31Jun 9, 2025Updated last year
- ☆58Oct 8, 2024Updated 2 years ago
- ☆18Jul 26, 2026Updated 3 months ago
- ☆17May 26, 2026Updated 5 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆45Apr 3, 2025Updated last year
- ☆10Jan 9, 2026Updated 9 months ago
- ☆31Jan 30, 2025Updated last year
- ☆10Nov 20, 2024Updated last year
- [ICCAD'26] Forbench: Symbolic Simulation Helps Make Your Testbench More Formal☆15Sep 8, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- SystemVerilog file list pruner☆19Oct 19, 2026Updated 2 weeks ago
- ☆50May 18, 2024Updated 2 years ago
- RTLScout is a agentic RTL optimization framework☆67Oct 26, 2026Updated last week
- ☆44Dec 21, 2025Updated 10 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated 2 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- ☆23Feb 9, 2026Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆91Aug 4, 2026Updated 3 months ago
- Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement☆37Sep 4, 2026Updated 2 months ago
- A comprehensive benchmark for AI-aided chip design☆46Aug 6, 2026Updated 2 months ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- The first large scale formally verified reasoning dataset for Verilog☆25May 16, 2025Updated last year
- AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.☆28Updated this week
- [NeurIPS 2026] Veri-Sure: Multi-Agent RTL Code Generation with Temporal Tracing, Slicing and Formal Verification☆28Oct 26, 2026Updated last week
- ☆11Feb 26, 2025Updated last year
- Verilog evaluation benchmark for large language model☆491Jul 14, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Hardware Agent☆36Updated this week
- ☆211Oct 17, 2024Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆19Jan 29, 2024Updated 2 years ago
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆29Sep 25, 2025Updated last year
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆41Jun 17, 2025Updated last year