Alternatives and similar repositories for schematics

Users that are interested in schematics are comparing it to the libraries listed below

• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆156Updated 3 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆118Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆162Updated this week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆102Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆150Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆198Updated this week
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆108Updated 10 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆87Updated 3 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆232Updated 2 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆139Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 9 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 2 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆178Updated last year
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated 2 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• antmicro / sv-bugpoint
  ☆30Updated last week
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆152Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆179Updated this week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆220Updated 3 weeks ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆83Updated 2 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆115Updated 4 months ago