Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
☆22Jul 8, 2013Updated 12 years ago
Alternatives and similar repositories for fpfma
Users that are interested in fpfma are comparing it to the libraries listed below
Sorting:
- ☆14Feb 24, 2025Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated last month
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- Example Codes for Snorkeling in Verilog Bay☆16Sep 9, 2016Updated 9 years ago
- ☆13Apr 24, 2015Updated 10 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- A Verilog implementation of a processor cache.☆36Dec 29, 2017Updated 8 years ago
- A Tcl-Library for scripted HDL generation☆17Apr 30, 2024Updated last year
- Virtual Platform for AWS FPGA support☆16Oct 19, 2018Updated 7 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆23Nov 7, 2022Updated 3 years ago
- Mathematical Functions in Verilog☆97Mar 7, 2021Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- This is a circular buffer controller used in FPGA.☆34Jan 12, 2016Updated 10 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- ☆19Aug 10, 2020Updated 5 years ago
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last week
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- ☆18Jul 11, 2021Updated 4 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated last month
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago