gilani / fpfma
Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
☆16Updated 11 years ago
Related projects: ⓘ
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- ☆21Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- eyeriss-chisel3☆35Updated 2 years ago
- CNN accelerator☆26Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- ☆35Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆26Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆23Updated 4 years ago
- ☆24Updated 5 years ago
- HLS for Networks-on-Chip☆27Updated 3 years ago
- ☆9Updated 3 months ago
- ☆12Updated this week
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- ☆23Updated 4 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆11Updated 8 years ago
- Documentation for the entire CGRAFlow☆17Updated 3 years ago
- Ratatoskr NoC Simulator☆18Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- The memory model was leveraged from micron.☆18Updated 6 years ago
- HLS implemented systolic array structure☆38Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- SRAM☆19Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆29Updated last year