gilani / fpfmaLinks
Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
☆22Updated 12 years ago
Alternatives and similar repositories for fpfma
Users that are interested in fpfma are comparing it to the libraries listed below
Sorting:
- ☆27Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last week
- HLS for Networks-on-Chip☆36Updated 4 years ago
- CNN accelerator☆27Updated 8 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- An example Hardware Processing Engine☆11Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- ☆30Updated last month
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆22Updated 9 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Public release☆56Updated 6 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago