Spector: An OpenCL FPGA Benchmark Suite
☆49Feb 2, 2019Updated 7 years ago
Alternatives and similar repositories for spector
Users that are interested in spector are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Apr 11, 2023Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆27Jun 18, 2020Updated 5 years ago
- The OpenDwarfs project provides a benchmark suite consisting of different computation/communication idioms, i.e., dwarfs, for state-of-ar…☆101Sep 18, 2019Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆170Nov 7, 2023Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Apr 1, 2020Updated 6 years ago
- NordVPN Threat Protection Pro™ • AdTake your cybersecurity to the next level. Block phishing, malware, trackers, and ads. Lightweight app that works with all browsers.
- Dataset for ML-guided Accelerator Design☆44Nov 18, 2024Updated last year
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- Extracts static code features from opencl kernels to be used for machine learning.☆10Apr 30, 2021Updated 4 years ago
- ☆18Mar 7, 2019Updated 7 years ago
- LLVM Plugin to Instrument Global Memory Accesses in CUDA Kernels☆10Jun 8, 2020Updated 5 years ago
- FPGA version of Rodinia in HLS C/C++☆42Dec 24, 2020Updated 5 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Oct 23, 2018Updated 7 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆50Mar 31, 2026Updated last week
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- ☆42Oct 10, 2025Updated 6 months ago
- Blaze runtime system that support efficient accelerator integration for big data.☆24Mar 23, 2017Updated 9 years ago
- ☆12Dec 17, 2023Updated 2 years ago
- ☆33Dec 16, 2021Updated 4 years ago
- ☆12Nov 19, 2022Updated 3 years ago
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- Qfsm is a graphical tool for designing finite state machine, written in C++ using the Qt library☆12Nov 19, 2018Updated 7 years ago
- ordspecsim: The Swarm architecture simulator☆24Feb 15, 2023Updated 3 years ago
- Tooling to use the Pynq Board somewhat nicely☆13Dec 5, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SDAccel Examples☆362May 20, 2022Updated 3 years ago
- FOundation of stXXl and thriLL☆14Jan 24, 2024Updated 2 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- ☆88Jan 7, 2023Updated 3 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 10 months ago
- A benchmark suite for Graph Machine Learning☆19Oct 8, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆365Updated this week
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 4 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Folding@home GPU benchmark☆35Jan 9, 2023Updated 3 years ago
- A Dataflow library for graph analytics acceleration☆14Dec 15, 2015Updated 10 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- Artifact of paper "Exploiting Recent SIMD Architectural Advances for Irregular Applications"☆11Jun 23, 2016Updated 9 years ago
- Sample program to compare calculation performance between CPU and GPU☆16Oct 27, 2016Updated 9 years ago
- ☆19Nov 21, 2022Updated 3 years ago
- HLS-based Graph Processing Framework on FPGAs☆150Oct 11, 2022Updated 3 years ago