Liu-Cheng / graph_acceleratorLinks
Graph accelerator on FPGAs and ASICs
☆12Updated 6 years ago
Alternatives and similar repositories for graph_accelerator
Users that are interested in graph_accelerator are comparing it to the libraries listed below
Sorting:
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 6 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆18Updated 2 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 3 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- ☆20Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- NeuraChip Accelerator Simulator☆12Updated last year
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆24Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆16Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 3 years ago
- ☆25Updated 3 years ago
- Hybrid BFS on Xilinx Zynq☆18Updated 9 years ago
- ☆11Updated 3 years ago
- ☆66Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- agile hardware-software co-design☆47Updated 3 years ago
- ☆35Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- A Cycle-level simulator for M2NDP☆27Updated last month