Liu-Cheng / graph_acceleratorLinks
Graph accelerator on FPGAs and ASICs
☆11Updated 7 years ago
Alternatives and similar repositories for graph_accelerator
Users that are interested in graph_accelerator are comparing it to the libraries listed below
Sorting:
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- ☆13Updated 5 years ago
- A Dataflow library for graph analytics acceleration☆14Updated 9 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆55Updated 4 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Updated 5 months ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- ☆68Updated 4 years ago
- 3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit (MICRO 2022)☆18Updated 2 years ago
- ☆20Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Updated 3 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆44Updated 2 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆58Updated 6 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆31Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆37Updated 3 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆25Updated 11 months ago
- ☆29Updated 4 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- agile hardware-software co-design☆52Updated 3 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 2 months ago
- This is a processing-in-memory simulator which models 3D-stacked memory within gem5. Also includes the workloads used for IMPICA (In-Memo…☆48Updated 8 years ago