CMU-SAFARI / VAMPIRE
An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 paper by Ghose et al. (https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18_pomacs18.pdf)
☆38Updated 6 years ago
Alternatives and similar repositories for VAMPIRE:
Users that are interested in VAMPIRE are comparing it to the libraries listed below
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆53Updated 3 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆69Updated 5 years ago
- ☆91Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- Fast and accurate DRAM power and energy estimation tool☆151Updated last week
- ☆35Updated 3 years ago
- ☆26Updated 11 months ago
- Release of stream-specialization software/hardware stack.☆121Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- CGRA Compilation Framework☆83Updated last year
- ☆25Updated 4 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- gem5 repository to study chiplet-based systems☆70Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆120Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- CGRA framework with vectorization support.☆28Updated this week
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆48Updated 3 months ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆15Updated 8 years ago
- An Open-Source Tool for CGRA Accelerators☆59Updated 2 months ago
- ☆86Updated last year
- ☆57Updated last year