KastnerRG / Spector-HLSLinks
Contains FPGA benchmarks for Vivado HLS and Catapult HLS
☆26Updated 5 years ago
Alternatives and similar repositories for Spector-HLS
Users that are interested in Spector-HLS are comparing it to the libraries listed below
Sorting:
- ☆27Updated last year
- ☆27Updated 5 years ago
- DASS HLS Compiler☆29Updated last year
- CNN accelerator☆27Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- ☆15Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 11 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Public release☆57Updated 6 years ago
- FPU Generator☆20Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 6 months ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 2 weeks ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆123Updated 2 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 9 years ago