bespoke-silicon-group / bsg_bladerunnerView external linksLinks
Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
☆44Jun 16, 2025Updated 8 months ago
Alternatives and similar repositories for bsg_bladerunner
Users that are interested in bsg_bladerunner are comparing it to the libraries listed below
Sorting:
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Aug 29, 2025Updated 5 months ago
- Domain-Specific Architecture Generator 2☆22Oct 2, 2022Updated 3 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆277Jan 10, 2026Updated last month
- ☆62Updated this week
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 3 years ago
- Next generation CGRA generator☆118Feb 4, 2026Updated last week
- ☆11Oct 28, 2021Updated 4 years ago
- ☆22Feb 18, 2025Updated 11 months ago
- ☆11Aug 4, 2022Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- ☆24Nov 10, 2020Updated 5 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- Polyite: Iterative Schedule Optimization for Parallelization in the Polyhedron Model☆12Jan 19, 2020Updated 6 years ago
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- ☆11Mar 16, 2022Updated 3 years ago
- ☆16May 10, 2019Updated 6 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- AMC: Asynchronous Memory Compiler☆52Jun 29, 2020Updated 5 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- ☆13Nov 29, 2024Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- A Specification and a Library for Data Exchange in Polyhedral Compilation Tools☆32Jul 19, 2024Updated last year
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 10 months ago
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆33Oct 6, 2022Updated 3 years ago
- ☆82Feb 7, 2025Updated last year
- SmoothE: Differentiable E-Graph Extraction (ASPLOS'25 Best Paper)☆31Jan 15, 2026Updated last month
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Dec 6, 2020Updated 5 years ago
- Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNs (MLSys'25)☆17Apr 4, 2025Updated 10 months ago
- CPUs☆16Dec 21, 2020Updated 5 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Mar 17, 2022Updated 3 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- OFS Platform Components☆19May 28, 2025Updated 8 months ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- SmartNIC☆14Dec 13, 2018Updated 7 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago