bespoke-silicon-group / bsg_bladerunnerLinks
Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
☆41Updated last week
Alternatives and similar repositories for bsg_bladerunner
Users that are interested in bsg_bladerunner are comparing it to the libraries listed below
Sorting:
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated 2 weeks ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆34Updated last month
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆59Updated last week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 8 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆33Updated last week
- DASS HLS Compiler☆29Updated last year
- ☆15Updated 4 years ago
- ☆24Updated 4 years ago
- ☆91Updated last year
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 2 weeks ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆28Updated 5 months ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- HeteroCL-MLIR dialect for accelerator design☆41Updated 9 months ago
- A hardware synthesis framework with multi-level paradigm☆39Updated 5 months ago
- ☆65Updated last week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago