Open, Modular, Deep Learning Accelerator
☆329Apr 10, 2024Updated last year
Alternatives and similar repositories for tvm-vta
Users that are interested in tvm-vta are comparing it to the libraries listed below
Sorting:
- Berkeley's Spatial Array Generator☆1,225Updated this week
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 2 months ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆341Apr 20, 2024Updated last year
- ☆43Mar 31, 2025Updated 11 months ago
- Automatic Schedule Exploration and Optimization Framework for Tensor Computations☆182Apr 25, 2022Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Updated this week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,149Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆154Feb 18, 2026Updated last week
- ☆19Dec 3, 2019Updated 6 years ago
- ☆37Jun 1, 2022Updated 3 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆871Jan 31, 2026Updated last month
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆89Mar 26, 2023Updated 2 years ago
- ☆657Jan 13, 2021Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆49Jan 2, 2025Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆239Dec 8, 2022Updated 3 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆218Dec 22, 2020Updated 5 years ago
- ☆1,908Updated this week
- Next generation CGRA generator☆118Feb 14, 2026Updated 2 weeks ago
- Open source machine learning accelerators☆397Mar 24, 2024Updated last year
- A home for the final text of all TVM RFCs.☆109Sep 24, 2024Updated last year
- RTL, Cmodel, and testbench for NVDLA☆2,025Mar 2, 2022Updated 4 years ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,056Nov 8, 2025Updated 3 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆255Oct 6, 2022Updated 3 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆443Dec 2, 2019Updated 6 years ago
- Release of stream-specialization software/hardware stack.☆120May 5, 2023Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆293Oct 30, 2025Updated 4 months ago
- Open Machine Learning Compiler Framework☆13,142Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- ☆367Sep 12, 2025Updated 5 months ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆114Jan 4, 2023Updated 3 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆490Nov 27, 2025Updated 3 months ago
- ☆16Oct 2, 2019Updated 6 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Feb 20, 2026Updated last week
- chisel tutorial exercises and answers☆747Jan 6, 2022Updated 4 years ago
- Algorithmic C Machine Learning Library☆26Jan 6, 2026Updated last month