Open, Modular, Deep Learning Accelerator
☆367Apr 10, 2024Updated 2 years ago
Alternatives and similar repositories for tvm-vta
Users that are interested in tvm-vta are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Berkeley's Spatial Array Generator☆1,503Updated this week
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆212Jun 25, 2020Updated 6 years ago
- ☆20Dec 3, 2019Updated 6 years ago
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)☆340Apr 20, 2024Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆68Sep 24, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆73Feb 16, 2023Updated 3 years ago
- Automatic Schedule Exploration and Optimization Framework for Tensor Computations☆184Apr 25, 2022Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Sep 19, 2026Updated 3 weeks ago
- Repository to host and maintain SCALE-Sim code☆530Jun 28, 2026Updated 3 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆247Dec 8, 2022Updated 3 years ago
- Open source machine learning accelerators☆400Mar 24, 2024Updated 2 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆240Dec 22, 2025Updated 9 months ago
- ☆2,303Updated this week
- ☆17Oct 2, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,418Updated this week
- RTL, Cmodel, and testbench for NVDLA☆2,180Mar 2, 2022Updated 4 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆452Dec 2, 2019Updated 6 years ago
- Open Machine Learning Compiler Framework☆13,823Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆956Updated this week
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆115Jan 4, 2023Updated 3 years ago
- ☆675Jan 13, 2021Updated 5 years ago
- ☆46Mar 31, 2025Updated last year
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆227Dec 22, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆528Jul 26, 2026Updated 2 months ago
- Allo Accelerator Design and Programming Framework (PLDI'24)☆413Sep 30, 2026Updated last week
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆390Jan 20, 2025Updated last year
- Release of stream-specialization software/hardware stack.☆127May 5, 2023Updated 3 years ago
- This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning an…☆2,128Mar 30, 2026Updated 6 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆303Sep 2, 2026Updated last month
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆265Oct 6, 2022Updated 4 years ago
- A Toy-Purpose TPU Simulator☆24Jun 7, 2024Updated 2 years ago
- Vitis HLS Library for FINN☆229Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Next generation CGRA generator☆119Updated this week
- Dataflow compiler for QNN inference on FPGAs☆1,080Updated this week
- A machine learning accelerator core designed for energy-efficient AI at the edge.☆2,589Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆552Updated this week
- Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"☆292Jun 2, 2024Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆167Jun 17, 2026Updated 3 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆178Mar 12, 2026Updated 6 months ago