tensil-ai / tensilLinks
Open source machine learning accelerators
☆384Updated last year
Alternatives and similar repositories for tensil
Users that are interested in tensil are comparing it to the libraries listed below
Sorting:
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆681Updated 7 years ago
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆513Updated 4 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆173Updated this week
- Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.☆257Updated 4 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆213Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆194Updated 6 years ago
- Open, Modular, Deep Learning Accelerator☆298Updated last year
- Dataflow QNN inference accelerator examples on FPGAs☆224Updated 4 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆490Updated 6 years ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆847Updated 6 months ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆422Updated 3 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- Vitis HLS LLVM source code and examples☆393Updated 9 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆343Updated 5 months ago
- ☆200Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆518Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆276Updated 3 months ago
- Research and Materials on Hardware implementation of Transformer Model☆275Updated 5 months ago
- ☆98Updated last year
- Berkeley's Spatial Array Generator☆1,010Updated 3 months ago
- VeeR EL2 Core☆292Updated 2 weeks ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆152Updated 2 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆429Updated 5 years ago
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- ☆334Updated 10 months ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆506Updated 8 months ago
- ☆284Updated this week