Open source machine learning accelerators
☆399Mar 24, 2024Updated 2 years ago
Alternatives and similar repositories for tensil
Users that are interested in tensil are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Dataflow compiler for QNN inference on FPGAs☆1,017Jul 1, 2026Updated last week
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆210Jun 25, 2020Updated 6 years ago
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆556Feb 26, 2026Updated 4 months ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆74Nov 7, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago
- ☆68Apr 30, 2025Updated last year
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆237Dec 22, 2025Updated 6 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 4 months ago
- Open, Modular, Deep Learning Accelerator☆353Apr 10, 2024Updated 2 years ago
- (System)Verilog to Chisel translator☆121May 20, 2022Updated 4 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆228Apr 22, 2019Updated 7 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆773Dec 6, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Berkeley's Spatial Array Generator☆1,382Jun 30, 2026Updated last week
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆387Jan 20, 2025Updated last year
- A DSL for Systolic Arrays☆86Dec 14, 2018Updated 7 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆416Jun 25, 2026Updated 2 weeks ago
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- ☆18Jan 22, 2025Updated last year
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 4 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆63Dec 3, 2021Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,309Jun 26, 2026Updated last week
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- PyTorch model to RTL flow for low latency inference☆131Mar 15, 2024Updated 2 years ago
- high-performance RTL simulator☆194Jun 19, 2024Updated 2 years ago
- Machine learning on FPGAs using HLS☆2,049Updated this week
- Dataflow QNN inference accelerator examples on FPGAs☆260Mar 10, 2026Updated 3 months ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆20Jan 21, 2022Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- SpinalHDL Hardware Math Library☆102Jul 12, 2024Updated last year
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆76Dec 29, 2025Updated 6 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆149Dec 25, 2019Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆14Aug 26, 2021Updated 4 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago