Alternatives and similar repositories for tensil

Users that are interested in tensil are comparing it to the libraries listed below

• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆653Updated 7 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆165Updated 4 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆373Updated 3 weeks ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆957Updated last month
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 5 years ago
• ztachip / ztachip
  Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
  ☆256Updated 2 months ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆217Updated 2 months ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆221Updated 2 years ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆345Updated 4 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆216Updated 6 years ago
• google / CFU-Playground
  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…
  ☆503Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆319Updated 4 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆221Updated last year
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆338Updated last year
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆269Updated last month
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated this week
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆199Updated 3 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆236Updated last year
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆259Updated last year
• apache / tvm-vta
  Open, Modular, Deep Learning Accelerator
  ☆288Updated last year
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆836Updated 4 months ago
• ucb-bar / berkeley-hardfloat
  ☆326Updated 8 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆224Updated last year
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆146Updated last year
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆389Updated 7 months ago
• fastmachinelearning / hls4ml-tutorial
  Tutorial notebooks for hls4ml
  ☆341Updated last week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆429Updated 2 weeks ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆126Updated last year