tensil-ai / tensil
Open source machine learning accelerators
☆378Updated last year
Alternatives and similar repositories for tensil
Users that are interested in tensil are comparing it to the libraries listed below
Sorting:
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆497Updated last month
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆370Updated this week
- Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.☆256Updated last month
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 4 months ago
- Open, Modular, Deep Learning Accelerator☆286Updated last year
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆418Updated 5 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆430Updated 7 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆253Updated this week
- Small-scale Tensor Processing Unit built on an FPGA☆183Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing☆338Updated last year
- Berkeley's Spatial Array Generator☆946Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆410Updated last week
- Dataflow QNN inference accelerator examples on FPGAs☆213Updated last month
- DPU on PYNQ☆220Updated last year
- PyTorch model to RTL flow for low latency inference☆126Updated last year
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆464Updated 6 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆340Updated 3 months ago
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆829Updated 4 months ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆271Updated 5 years ago
- IC implementation of Systolic Array for TPU☆239Updated 6 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆209Updated 5 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆145Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆190Updated 4 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆212Updated 6 years ago
- NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network☆350Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆268Updated 3 weeks ago
- ☆89Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 3 months ago