jinhachung / tptpu-simLinks
A Toy-Purpose TPU Simulator
☆19Updated last year
Alternatives and similar repositories for tptpu-sim
Users that are interested in tptpu-sim are comparing it to the libraries listed below
Sorting:
- ☆35Updated 6 months ago
- ☆36Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆43Updated 9 months ago
- ☆31Updated 11 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆28Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last week
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆18Updated 2 months ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆38Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆31Updated last year
- ☆25Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆39Updated 3 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated last week
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆28Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆51Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆64Updated 9 months ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆57Updated 6 years ago
- ☆97Updated last year
- agile hardware-software co-design☆51Updated 3 years ago