Alternatives and similar repositories for AXI4_Interconnect

Users that are interested in AXI4_Interconnect are comparing it to the libraries listed below

• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 4 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆224Updated 2 years ago
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆177Updated last month
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆132Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆41Updated 3 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆28Updated 2 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆128Updated 7 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆182Updated 7 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆155Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆63Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆59Updated last year
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆80Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆68Updated last year
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆108Updated 9 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 7 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆88Updated 3 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆109Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆64Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆82Updated 7 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆46Updated 6 years ago