dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
☆313Updated 10 months ago
Alternatives and similar repositories for async_fifo:
Users that are interested in async_fifo are comparing it to the libraries listed below
- AMBA AXI VIP☆387Updated 8 months ago
- AXI interface modules for Cocotb☆244Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆423Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆192Updated last year
- AMBA bus lecture material☆410Updated 5 years ago
- uvm AXI BFM(bus functional model)☆240Updated 11 years ago
- Bus bridges and other odds and ends☆523Updated last month
- Verilog UART☆459Updated 2 weeks ago
- Common SystemVerilog components☆587Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆790Updated 2 weeks ago
- Opensource DDR3 Controller☆279Updated this week
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆137Updated 3 weeks ago
- Various HDL (Verilog) IP Cores☆751Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Awesome ASIC design verification☆287Updated 3 years ago
- Reference examples and short projects using UVM Methodology☆260Updated 2 years ago
- Verilog I2C interface for FPGA implementation☆589Updated 2 weeks ago
- The UVM written in Python☆414Updated 2 months ago
- UVM 1.2 port to Python☆250Updated last month
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆166Updated 6 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆145Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,233Updated 2 weeks ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆405Updated this week
- Basic RISC-V Test SoC☆116Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- training labs and examples☆415Updated 2 years ago
- SPI Master for FPGA - VHDL and Verilog☆275Updated last year