dpretet / async_fifoLinks
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
☆410Updated 4 months ago
Alternatives and similar repositories for async_fifo
Users that are interested in async_fifo are comparing it to the libraries listed below
Sorting:
- A DDR3 memory controller in Verilog for various FPGAs☆548Updated 4 years ago
- AXI interface modules for Cocotb☆305Updated 3 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆235Updated 2 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆568Updated 2 weeks ago
- AMBA bus lecture material☆497Updated 5 years ago
- AMBA AXI VIP☆438Updated last year
- Verilog UART☆528Updated 10 months ago
- Bus bridges and other odds and ends☆623Updated 9 months ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Awesome ASIC design verification☆341Updated 3 years ago
- Reference examples and short projects using UVM Methodology☆287Updated 3 years ago
- Verilog I2C interface for FPGA implementation☆673Updated 10 months ago
- uvm AXI BFM(bus functional model)☆264Updated 12 years ago
- The UVM written in Python☆492Updated this week
- Common SystemVerilog components☆694Updated 3 weeks ago
- An AXI4 crossbar implementation in SystemVerilog☆203Updated 4 months ago
- Verilog AXI stream components for FPGA implementation☆854Updated 10 months ago
- Pipeline FFT Implementation in Verilog HDL☆153Updated 6 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- training labs and examples☆445Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆451Updated 8 months ago
- Verilog UART☆188Updated 12 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆593Updated 4 years ago
- Verilog SDRAM memory controller☆351Updated 8 years ago
- Various HDL (Verilog) IP Cores☆859Updated 4 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆204Updated 8 years ago
- SPI Master for FPGA - VHDL and Verilog☆320Updated 2 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆190Updated 7 years ago
- lowRISC Style Guides☆474Updated 2 months ago
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago