dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
☆294Updated 9 months ago
Alternatives and similar repositories for async_fifo:
Users that are interested in async_fifo are comparing it to the libraries listed below
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆180Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆396Updated 3 years ago
- AXI interface modules for Cocotb☆226Updated last year
- AMBA bus lecture material☆401Updated 5 years ago
- AMBA AXI VIP☆371Updated 7 months ago
- uvm AXI BFM(bus functional model)☆236Updated 11 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆115Updated 3 years ago
- AXI DMA 32 / 64 bits☆105Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆130Updated 2 months ago
- Common SystemVerilog components☆560Updated 2 weeks ago
- Bus bridges and other odds and ends☆511Updated last week
- Awesome ASIC design verification☆277Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆769Updated 5 months ago
- Verilog UART☆437Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- Basic RISC-V Test SoC☆109Updated 5 years ago
- UVM 1.2 port to Python☆247Updated 10 months ago
- Reference examples and short projects using UVM Methodology☆254Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆142Updated 2 years ago
- Verilog I2C interface for FPGA implementation☆571Updated 6 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 7 months ago
- Various HDL (Verilog) IP Cores☆726Updated 3 years ago
- AXI总线连接器☆93Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆161Updated 6 years ago
- Opensource DDR3 Controller☆250Updated last week
- SPI Master for FPGA - VHDL and Verilog☆269Updated last year
- The UVM written in Python☆398Updated 2 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆94Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆178Updated 4 years ago
- Pipeline FFT Implementation in Verilog HDL☆92Updated 5 years ago