Alternatives and similar repositories for async_fifo:

Users that are interested in async_fifo are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆436Updated 3 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆393Updated 9 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆251Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆537Updated 2 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆198Updated last year
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆422Updated 5 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆796Updated last month
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆244Updated 11 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆599Updated 3 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆421Updated 3 weeks ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆119Updated 3 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆290Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆468Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆264Updated 2 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆773Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆418Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆310Updated 3 weeks ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆250Updated 2 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,249Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆600Updated last month
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆111Updated 10 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆142Updated this week
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆184Updated 4 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆279Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆185Updated 7 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆167Updated 6 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆167Updated this week
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆203Updated 8 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆144Updated last month