Alternatives and similar repositories for async_fifo

Users that are interested in async_fifo are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆492Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆208Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆408Updated last year
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆250Updated 12 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆493Updated 4 months ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆114Updated 10 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆448Updated 5 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆283Updated 3 weeks ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆309Updated 3 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆436Updated last week
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆275Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆426Updated 2 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆625Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated this week
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated 3 weeks ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆812Updated 4 months ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆199Updated 4 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆296Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆100Updated 5 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆556Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆143Updated 6 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆173Updated 6 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆203Updated last year
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆218Updated last year