Alternatives and similar repositories for async_fifo

Users that are interested in async_fifo are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆296Updated last month
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆459Updated this week
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆474Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆224Updated 2 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆511Updated 8 months ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆132Updated 4 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆602Updated 6 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆329Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆655Updated 8 months ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆282Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆435Updated 3 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆142Updated 6 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆479Updated this week
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆184Updated 7 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆838Updated 8 months ago
• jamieiles / uart
  Verilog UART
  ☆185Updated 12 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆207Updated 5 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated last week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆178Updated 2 months ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆202Updated 8 years ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆575Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• raysalemi / Python4RTLVerification
  ☆168Updated 3 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago