Alternatives and similar repositories for async_fifo

Users that are interested in async_fifo are comparing it to the libraries listed below

• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆542Updated 4 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆304Updated 2 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆434Updated last year
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆490Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆234Updated 2 years ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆536Updated last month
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆613Updated 8 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆517Updated 10 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆850Updated 10 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆689Updated last week
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆264Updated 12 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆153Updated 6 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆489Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆665Updated 10 months ago
• VerificationExcellence / UVMReference
  Reference examples and short projects using UVM Methodology
  ☆286Updated 3 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆337Updated 3 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆442Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆134Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆196Updated 3 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆279Updated 5 years ago
• jamieiles / uart
  Verilog UART
  ☆187Updated 12 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆189Updated 7 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆402Updated 6 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆369Updated 2 weeks ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆218Updated last year
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆854Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆159Updated 10 months ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆166Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆212Updated 5 years ago