dpretet / async_fifoLinks
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
☆363Updated last year
Alternatives and similar repositories for async_fifo
Users that are interested in async_fifo are comparing it to the libraries listed below
Sorting:
- AXI interface modules for Cocotb☆276Updated last year
- AMBA AXI VIP☆416Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆502Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆214Updated 2 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆345Updated 2 weeks ago
- AMBA bus lecture material☆456Updated 5 years ago
- Awesome ASIC design verification☆316Updated 3 years ago
- Reference examples and short projects using UVM Methodology☆278Updated 3 years ago
- uvm AXI BFM(bus functional model)☆253Updated 12 years ago
- Verilog UART☆502Updated 5 months ago
- AXI DMA 32 / 64 bits☆119Updated 11 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆129Updated 4 years ago
- The UVM written in Python☆449Updated last month
- Bus bridges and other odds and ends☆582Updated 4 months ago
- Common SystemVerilog components☆649Updated this week
- Verilog AXI stream components for FPGA implementation☆819Updated 5 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆175Updated 7 years ago
- UVM 1.2 port to Python☆253Updated 6 months ago
- An AXI4 crossbar implementation in SystemVerilog☆169Updated this week
- Source code repo for UVM Tutorial for Candy Lovers☆197Updated 8 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆564Updated 3 years ago
- Verilog UART☆178Updated 12 years ago
- Verilog I2C interface for FPGA implementation☆640Updated 5 months ago
- This is the main repository for all the examples for the book Practical UVM☆201Updated 4 years ago
- Xilinx Tcl Store☆367Updated last week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆147Updated 7 years ago
- Pipeline FFT Implementation in Verilog HDL☆128Updated 6 years ago
- Opensource DDR3 Controller☆381Updated 2 months ago
- Verilog SDRAM memory controller☆339Updated 8 years ago