Alternatives and similar repositories for core_dbg_bridge

Users that are interested in core_dbg_bridge are comparing it to the libraries listed below

• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆78Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆93Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆17Updated 2 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆80Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆52Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆46Updated 9 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 7 months ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆59Updated 9 years ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆48Updated 2 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆39Updated last week
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆40Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆15Updated 10 years ago
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago