UART -> AXI Bridge
☆74Jul 1, 2021Updated 4 years ago
Alternatives and similar repositories for core_dbg_bridge
Users that are interested in core_dbg_bridge are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB -> AXI Debug Bridge☆44Jun 5, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Wishbone SATA Controller☆26Oct 16, 2025Updated 7 months ago
- AXI总线连接器☆106Mar 26, 2020Updated 6 years ago
- AXI Interconnect☆56Aug 20, 2021Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Ethernet MAC 10/100 Mbps☆37Oct 31, 2021Updated 4 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 6 years ago
- Fixed Point Math Library for Verilog☆150Jul 17, 2014Updated 11 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆99Jun 6, 2020Updated 5 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,052Feb 27, 2025Updated last year
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆17Sep 5, 2023Updated 2 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆34Jun 5, 2021Updated 4 years ago
- SDRAM controller with AXI4 interface☆104Aug 8, 2019Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆85Oct 6, 2022Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆230May 15, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆12Jul 20, 2022Updated 3 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆25Nov 7, 2022Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- ☆32Jul 9, 2025Updated 10 months ago
- AMBA bus generator including AXI, AHB, and APB☆123Jul 29, 2021Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆57Oct 18, 2023Updated 2 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- AHB DMA 32 / 64 bits☆61Jul 17, 2014Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- ☆31Apr 1, 2017Updated 9 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆43Jan 18, 2024Updated 2 years ago
- AXI DMA 32 / 64 bits☆129Jul 17, 2014Updated 11 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆11Jun 2, 2021Updated 4 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago