ultraembedded / core_dbg_bridgeLinks
UART -> AXI Bridge
☆61Updated 3 years ago
Alternatives and similar repositories for core_dbg_bridge
Users that are interested in core_dbg_bridge are comparing it to the libraries listed below
Sorting:
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- AXI Interconnect☆49Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆72Updated 2 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆55Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆67Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- ☆36Updated 9 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆102Updated 3 years ago
- ☆26Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆73Updated last year
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago