ultraembedded / core_dbg_bridgeLinks
UART -> AXI Bridge
☆63Updated 4 years ago
Alternatives and similar repositories for core_dbg_bridge
Users that are interested in core_dbg_bridge are comparing it to the libraries listed below
Sorting:
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 6 months ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- AXI Interconnect☆52Updated 4 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated 2 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- ☆74Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆37Updated last year
- ☆27Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆64Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆88Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆35Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- ☆78Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- UART models for cocotb☆29Updated last week