AXI, AXI stream, Ethernet, and PCIe components in System Verilog
☆989Aug 28, 2026Updated last month
Alternatives and similar repositories for taxi
Users that are interested in taxi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Ethernet components for FPGA implementation☆3,136Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,163Feb 27, 2025Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆2,503Jul 5, 2024Updated 2 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,735Sep 24, 2026Updated last month
- Verilog PCI express components☆1,672Apr 26, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Opensource DDR3 Controller☆490Sep 12, 2026Updated last month
- Open Logic FPGA Standard Library☆1,029Updated this week
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- Common SystemVerilog components☆810Sep 18, 2026Updated last month
- Verilog AXI stream components for FPGA implementation☆923Feb 27, 2025Updated last year
- Build your hardware, easily!☆4,173Updated this week
- AXI interface modules for Cocotb☆368Aug 24, 2026Updated 2 months ago
- Ethernet interface modules for Cocotb☆83Aug 28, 2026Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆495Oct 17, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HDL libraries and projects☆2,040Updated this week
- Bus bridges and other odds and ends☆712Sep 11, 2026Updated last month
- Small footprint and configurable PCIe core☆739Oct 12, 2026Updated last week
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆30Jul 5, 2026Updated 3 months ago
- Small footprint and configurable Ethernet core☆309Updated this week
- cocotb: Python-based chip (RTL) verification☆2,552Updated this week
- PCI express simulation framework for Cocotb☆213Aug 25, 2026Updated 2 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆220Oct 17, 2026Updated last week
- Parametric AXI4 crossbar in SystemVerilog☆249May 25, 2026Updated 5 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆90Jun 27, 2022Updated 4 years ago
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,478Updated this week
- AMD OpenNIC Project Overview☆349Dec 20, 2022Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆866Sep 14, 2023Updated 3 years ago
- 10Gb Ethernet Switch☆279Sep 17, 2026Updated last month
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,970Sep 23, 2026Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆248Updated this week
- Unit testing for cocotb☆177Oct 17, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆82Feb 5, 2022Updated 4 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆20Oct 23, 2023Updated 3 years ago
- Various HDL (Verilog) IP Cores☆937Jul 1, 2021Updated 5 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆134Updated this week
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆72Jan 10, 2024Updated 2 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆973Aug 3, 2026Updated 2 months ago