An AXI4 crossbar implementation in SystemVerilog
☆212Sep 2, 2025Updated 6 months ago
Alternatives and similar repositories for axi-crossbar
Users that are interested in axi-crossbar are comparing it to the libraries listed below
Sorting:
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆238Jul 16, 2023Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 3 years ago
- AMBA AXI VIP☆448Jun 28, 2024Updated last year
- General Purpose AXI Direct Memory Access☆62May 12, 2024Updated last year
- AMBA bus generator including AXI, AHB, and APB☆119Jul 29, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆1,970Feb 27, 2025Updated last year
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- UART -> AXI Bridge☆71Jul 1, 2021Updated 4 years ago
- HDL components to build a customized Wishbone crossbar switch☆14May 30, 2019Updated 6 years ago
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- VIP for AXI Protocol☆164May 24, 2022Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆269Feb 27, 2026Updated last week
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆39Nov 24, 2022Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆58Dec 31, 2019Updated 6 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆189Nov 18, 2024Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆197Updated this week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆424Feb 13, 2026Updated 3 weeks ago
- Common SystemVerilog components☆713Feb 26, 2026Updated last week
- AMBA bus lecture material☆512Jan 21, 2020Updated 6 years ago
- Bus bridges and other odds and ends☆644Apr 14, 2025Updated 10 months ago
- SDRAM controller with AXI4 interface☆103Aug 8, 2019Updated 6 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆149Updated this week
- Verification IP for APB protocol☆74Dec 18, 2020Updated 5 years ago
- AMBA 3 AHB UVM TB☆35Mar 21, 2019Updated 6 years ago
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago