Alternatives and similar repositories for axi-crossbar

Users that are interested in axi-crossbar are comparing it to the libraries listed below

• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆196Updated 3 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆259Updated 3 weeks ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆141Updated 7 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆185Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• RV-BOSC / OpenNoC
  ☆215Updated 6 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆97Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆117Updated 4 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆102Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆189Updated last week
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆150Updated 9 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆134Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆114Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆79Updated 7 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆144Updated 6 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆235Updated 2 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆67Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆93Updated 4 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 2 months ago
• ForrestBlue / cortexm0ds
  ☆73Updated 9 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆42Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆135Updated 10 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆100Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year