AXI interface modules for Cocotb
☆344Mar 13, 2026Updated 4 months ago
Alternatives and similar repositories for cocotbext-axi
Users that are interested in cocotbext-axi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PCI express simulation framework for Cocotb☆209Sep 8, 2025Updated 10 months ago
- Ethernet interface modules for Cocotb☆80Jun 20, 2026Updated last month
- Unit testing for cocotb☆174Apr 18, 2026Updated 3 months ago
- UART models for cocotb☆35Sep 7, 2025Updated 10 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆79Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- I2C models for cocotb☆46Mar 18, 2026Updated 4 months ago
- cocotb: Python-based chip (RTL) verification☆2,456Updated this week
- Verilog AXI stream components for FPGA implementation☆907Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,100Feb 27, 2025Updated last year
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 11 months ago
- Verilog PCI express components☆1,628Apr 26, 2024Updated 2 years ago
- The UVM written in Python☆561Updated this week
- ☆29Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- understanding of cocotb （In Chinese Only）☆22Jun 10, 2025Updated last year
- ☆17Feb 9, 2023Updated 3 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆127Oct 3, 2025Updated 9 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- ESnet general-purpose FPGA design library.☆14Jun 24, 2026Updated last month
- Verilog Ethernet components for FPGA implementation☆3,045Feb 27, 2025Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,638Updated this week
- ☆27Jun 12, 2022Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,405Jul 5, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Fully parametrizable combinatorial parallel LFSR/CRC module☆162Feb 27, 2025Updated last year
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆70Updated this week
- Code generation tool for control and status registers☆463Jul 16, 2026Updated last week
- cocotb code library☆13Dec 28, 2020Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆78Jul 14, 2026Updated 2 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆476Updated this week
- Verilog I2C interface for FPGA implementation☆710Feb 27, 2025Updated last year
- Examples for using pyuvm☆22Jun 5, 2024Updated 2 years ago
- Verilog digital signal processing components☆187Oct 30, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Common SystemVerilog components☆772Updated this week
- Bus bridges and other odds and ends☆688Jun 2, 2026Updated last month
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- Control and status register code generator toolchain☆201Jul 14, 2026Updated 2 weeks ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Jul 20, 2026Updated last week