Alternatives and similar repositories for riffa:

Users that are interested in riffa are comparing it to the libraries listed below

• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,231Updated 10 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆780Updated this week
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,624Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,216Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆745Updated 3 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆449Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆581Updated this week
• Digilent / vivado-library
  ☆602Updated 8 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,723Updated 3 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,253Updated 9 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆522Updated 3 weeks ago
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆532Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆420Updated 3 years ago
• bperez77 / xilinx_axidma
  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…
  ☆486Updated 2 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆235Updated last month
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆563Updated 6 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆307Updated 10 months ago
• fpgasystems / fpga-network-stack
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆790Updated 3 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,019Updated 2 weeks ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆908Updated last month
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆515Updated last week
• Xilinx / dma_ip_drivers
  Xilinx QDMA IP Drivers
  ☆612Updated 2 weeks ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆414Updated 2 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆570Updated last year
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,594Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆578Updated this week
• alexforencich / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆2,452Updated this week
• ucsdsysnet / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆189Updated 10 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆407Updated 5 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆852Updated last year