KastnerRG / riffa
The RIFFA development repository
☆777Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for riffa
- Verilog PCI express components☆1,141Updated 6 months ago
- Verilog AXI components for FPGA implementation☆1,521Updated 11 months ago
- Verilog AXI stream components for FPGA implementation☆746Updated 3 months ago
- Various HDL (Verilog) IP Cores☆710Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,115Updated this week
- Verilog I2C interface for FPGA implementation☆549Updated 4 months ago
- Bus bridges and other odds and ends☆491Updated 10 months ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆468Updated last year
- Verilog UART☆424Updated last year
- Verilog library for ASIC and FPGA designers☆1,195Updated 6 months ago
- ☆574Updated 4 months ago
- Must-have verilog systemverilog modules☆1,657Updated 2 weeks ago
- Example designs for FPGA Drive FMC☆221Updated this week
- A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…☆472Updated last year
- Common SystemVerilog components☆521Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆965Updated 4 months ago
- Xilinx QDMA IP Drivers☆577Updated 3 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆756Updated last week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆550Updated 6 years ago
- HDL libraries and projects☆1,533Updated this week
- Small footprint and configurable PCIe core☆484Updated this week
- ☆599Updated last week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆266Updated 6 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆371Updated 3 years ago
- AMBA bus lecture material☆380Updated 4 years ago
- Verilog Ethernet components for FPGA implementation☆2,321Updated 4 months ago
- The UVM written in Python☆374Updated 4 months ago
- Support for Rocket Chip on Zynq FPGAs☆397Updated 5 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆488Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,027Updated 2 months ago