KastnerRG / riffaLinks
The RIFFA development repository
☆840Updated last year
Alternatives and similar repositories for riffa
Users that are interested in riffa are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,396Updated last year
- Verilog AXI stream components for FPGA implementation☆817Updated 5 months ago
- Various HDL (Verilog) IP Cores☆823Updated 4 years ago
- Verilog AXI components for FPGA implementation☆1,783Updated 5 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,343Updated this week
- Verilog I2C interface for FPGA implementation☆637Updated 5 months ago
- Verilog UART☆499Updated 5 months ago
- ☆627Updated last week
- A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…☆507Updated 2 years ago
- HDL libraries and projects☆1,708Updated this week
- Bus bridges and other odds and ends☆576Updated 3 months ago
- Xilinx QDMA IP Drivers☆698Updated 5 months ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆659Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆498Updated 3 years ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆590Updated 7 years ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆979Updated 2 weeks ago
- Must-have verilog systemverilog modules☆1,816Updated this week
- Example designs for FPGA Drive FMC☆258Updated 6 months ago
- Verilog Ethernet components for FPGA implementation☆2,654Updated 5 months ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆842Updated last month
- Verilog library for ASIC and FPGA designers☆1,322Updated last year
- Small footprint and configurable PCIe core☆566Updated 3 weeks ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆359Updated last year
- Common SystemVerilog components☆642Updated last week
- Xilinx Tcl Store☆364Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,101Updated 2 months ago
- Verilog SDRAM memory controller☆337Updated 8 years ago
- Open source FPGA-based NIC and platform for in-network compute☆197Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆328Updated last month
- Support for Rocket Chip on Zynq FPGAs☆411Updated 6 years ago