KastnerRG / riffaLinks
The RIFFA development repository
☆835Updated last year
Alternatives and similar repositories for riffa
Users that are interested in riffa are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,359Updated last year
- Verilog AXI stream components for FPGA implementation☆810Updated 3 months ago
- Verilog AXI components for FPGA implementation☆1,746Updated 3 months ago
- Various HDL (Verilog) IP Cores☆813Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,308Updated this week
- Verilog UART☆490Updated 3 months ago
- Verilog I2C interface for FPGA implementation☆624Updated 3 months ago
- Must-have verilog systemverilog modules☆1,797Updated 2 months ago
- Bus bridges and other odds and ends☆568Updated 2 months ago
- Verilog library for ASIC and FPGA designers☆1,303Updated last year
- Xilinx QDMA IP Drivers☆683Updated 3 months ago
- ☆618Updated 11 months ago
- HDL libraries and projects☆1,675Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- Example designs for FPGA Drive FMC☆252Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,080Updated 3 weeks ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆967Updated last week
- Common SystemVerilog components☆629Updated this week
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆628Updated last year
- A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communicat…☆501Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆353Updated last year
- Verilog Ethernet components for FPGA implementation☆2,606Updated 3 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆581Updated 7 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆830Updated 3 months ago
- Support for Rocket Chip on Zynq FPGAs☆409Updated 6 years ago
- Random instruction generator for RISC-V processor verification☆1,135Updated 2 weeks ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆264Updated last week
- Xilinx Tcl Store☆359Updated 3 weeks ago
- Small footprint and configurable PCIe core☆558Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,300Updated this week