Alternatives and similar repositories for verilog_axi-interconnect:

Users that are interested in verilog_axi-interconnect are comparing it to the libraries listed below

• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆34Updated 2 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆59Updated 4 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆30Updated 2 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆24Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆26Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆40Updated 5 years ago
• freecores / apbi2c
  APB to I2C
  ☆39Updated 10 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆30Updated 4 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆48Updated 4 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆31Updated 3 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆21Updated 2 years ago
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆27Updated 6 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆85Updated last year
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆49Updated 11 months ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆41Updated 3 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆42Updated 4 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆96Updated 4 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆38Updated last year
• VimfulDang / APB-SPI-Controller-Verification
  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…
  ☆9Updated 2 months ago