adki / RTL-Design-For-FPGA
Engineering Program on RTL Design for FPGA Accelerator
☆27Updated 4 years ago
Alternatives and similar repositories for RTL-Design-For-FPGA:
Users that are interested in RTL-Design-For-FPGA are comparing it to the libraries listed below
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆51Updated this week
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆53Updated 4 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 2 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- ☆19Updated 10 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆100Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆24Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆30Updated last month
- Implementation of the PCIe physical layer☆33Updated last month
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated 2 weeks ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- ☆24Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Verilog RTL Design☆32Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- ☆29Updated 5 years ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆52Updated 4 years ago