adki / RTL-Design-For-FPGALinks
Engineering Program on RTL Design for FPGA Accelerator
☆29Updated 4 years ago
Alternatives and similar repositories for RTL-Design-For-FPGA
Users that are interested in RTL-Design-For-FPGA are comparing it to the libraries listed below
Sorting:
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆20Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆30Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- A reference book on System-on-Chip Design☆29Updated last year
- ☆41Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago