Alternatives and similar repositories for zynq_axi_ddr_barebone

Users that are interested in zynq_axi_ddr_barebone are comparing it to the libraries listed below

• antmicro / openssd-nvme
  ☆33Updated 4 years ago
• FDU-ME-ARC / NVMeCHA
  ☆19Updated 4 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆22Updated last week
• ntpt7921 / Verilog_UDP_TCP
  Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
  ☆13Updated 3 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆34Updated 4 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆19Updated 6 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆32Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• cudnn / USBtoMIPI
  - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA
  ☆12Updated 8 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆72Updated 8 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆60Updated 3 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆33Updated 7 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆54Updated last month
• yedk / arm_cortex_m0_xillinx
  基于arm cortex-m0内核的xillinx fpga sopc工程项目
  ☆13Updated 6 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆76Updated last year
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated last month
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• For-up / SEA-S7Guess
  SEA-S7_gesture recognition
  ☆17Updated 5 years ago
• DeamonYang / FPGA_SDR
  软件无线电，使用FPGA进行正交解调。
  ☆22Updated 6 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆22Updated 2 years ago