xycfwrj / zynq_axi_ddr_barebone
minimal code to access ps DDR from PL
☆19Updated 5 years ago
Alternatives and similar repositories for zynq_axi_ddr_barebone:
Users that are interested in zynq_axi_ddr_barebone are comparing it to the libraries listed below
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- ☆14Updated 3 years ago
- 基于FPGA的FFT☆12Updated 6 years ago
- ☆18Updated 3 years ago
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- ☆28Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆46Updated 7 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- ☆16Updated 5 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- Verification of Ethernet Switch System Verilog☆11Updated 8 years ago
- FPGA Technology Exchange Group相关文件管理☆43Updated last year
- Xilinx IP repository☆13Updated 6 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆12Updated 5 years ago
- SEA-S7_gesture recognition☆15Updated 4 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- kintex7 ov13850 fpga mipi camera☆18Updated last year
- FPGA和USB3.0桥片实现USB3.0通信☆61Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- FPGA纯逻辑实现modbus通信☆17Updated 2 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆25Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆24Updated 8 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆68Updated 9 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- FIR,FFT based on Verilog☆13Updated 7 years ago