sysu-eda / DeepRL-Scheduling
A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
☆14Updated 3 years ago
Alternatives and similar repositories for DeepRL-Scheduling:
Users that are interested in DeepRL-Scheduling are comparing it to the libraries listed below
- IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis☆24Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆12Updated 3 years ago
- Benchmarks for High-Level Synthesis☆10Updated last year
- ☆13Updated 4 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated last year
- LLM4HWDesign Starting Toolkit☆17Updated 3 months ago
- ☆12Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆20Updated 2 years ago
- Pathfinder routing algorithm practice☆12Updated 7 years ago
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 4 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 10 months ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- ☆22Updated 8 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- ☆12Updated 5 months ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- ☆46Updated 3 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Convert C files into Verilog☆16Updated 5 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆29Updated 4 years ago
- ☆26Updated 7 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆31Updated 4 years ago
- ☆16Updated last year
- DASS HLS Compiler☆27Updated last year
- SmartNIC☆14Updated 6 years ago
- ☆32Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago