Alternatives and similar repositories for DeepRL-Scheduling

Users that are interested in DeepRL-Scheduling are comparing it to the libraries listed below

• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated 2 years ago
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• wincle626 / HLS_Legup
  ☆29Updated 8 years ago
• cornell-zhang / datuner
  DATuner Repository
  ☆17Updated 7 years ago
• lydiawunan / IronMan
  IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis
  ☆27Updated 3 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆19Updated 6 years ago
• daitoto / EDA-wiki
  EDA wiki
  ☆53Updated 2 years ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis
  ☆24Updated 3 weeks ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 6 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated 2 years ago
• Reconfigurable-Computing / HLStoFPGA
  ☆12Updated 3 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆38Updated 3 months ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆23Updated 2 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆32Updated 2 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated 2 years ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 4 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated last year
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆14Updated 3 years ago
• levibyte / pyqt_genetic_algo
  genetic algorithm usage for routing optimization ( pyqt )
  ☆15Updated 6 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆14Updated 8 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 5 months ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 8 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆32Updated 6 years ago
• IntelLabs / parsac
  This is the implementation of the Parallel Simulated Annealing with Constraints (PARSAC) algorithm
  ☆18Updated 5 months ago