TUD-ADS / HiFlipVX
☆16Updated 2 years ago
Alternatives and similar repositories for HiFlipVX
Users that are interested in HiFlipVX are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆71Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆93Updated 11 months ago
- ☆57Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- Tutorials on HLS Design☆51Updated 5 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆14Updated last year
- Algorithmic C Machine Learning Library☆23Updated 5 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 8 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆35Updated 4 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 6 months ago
- PYNQ Composabe Overlays☆71Updated 11 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆35Updated 3 weeks ago
- ☆57Updated last year
- ☆59Updated 2 weeks ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆44Updated last month
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated 7 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- DASS HLS Compiler☆29Updated last year
- ☆27Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago