TUD-ADS / HiFlipVXLinks
☆17Updated 3 years ago
Alternatives and similar repositories for HiFlipVX
Users that are interested in HiFlipVX are comparing it to the libraries listed below
Sorting:
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Algorithmic C Machine Learning Library☆26Updated 3 weeks ago
- ☆72Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 weeks ago
- NeuraLUT-Assemble☆46Updated 3 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆38Updated last month
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- ☆28Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated 2 weeks ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- ☆65Updated 7 months ago
- Train and deploy LUT-based neural networks on FPGAs☆102Updated last year
- Tutorials on HLS Design☆52Updated 5 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆45Updated last month
- ☆38Updated 8 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆36Updated 4 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆72Updated 8 months ago
- ☆15Updated 5 months ago
- ☆64Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- ☆22Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆47Updated last year