AEW2015 / fpga-colabLinks
FPGA examples on Google Colab
☆22Updated last year
Alternatives and similar repositories for fpga-colab
Users that are interested in fpga-colab are comparing it to the libraries listed below
Sorting:
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated 2 months ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 3 months ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆60Updated this week
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆11Updated last week
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆67Updated 8 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- ☆59Updated 3 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Fabric generator and CAD tools graphical frontend☆13Updated 2 weeks ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- ☆32Updated 4 months ago
- Python interface to PCIE☆39Updated 7 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 10 months ago
- Spen's Official OpenOCD Mirror☆50Updated 2 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆38Updated 3 weeks ago
- ☆33Updated 2 years ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated last week