AEW2015 / fpga-colab
FPGA examples on Google Colab
☆18Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for fpga-colab
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆27Updated 3 years ago
- A padring generator for ASICs☆22Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆48Updated last week
- Bitstream relocation and manipulation tool.☆40Updated last year
- ☆29Updated 2 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆14Updated 3 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- ☆36Updated 2 years ago
- ☆29Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- ☆39Updated last year
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Fixed point math library for SystemVerilog☆15Updated last week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- A compact, configurable RISC-V core☆11Updated last week
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- SAR ADC on tiny tapeout☆35Updated last week
- ☆40Updated 8 months ago
- Drawio => VHDL and Verilog☆51Updated last year
- sample VCD files☆36Updated 9 months ago
- A Fully Open-Source Verilog-to-PCB Flow☆17Updated 4 months ago
- ☆31Updated last week