haifengch / axi_interconnectLinks
☆23Updated 2 months ago
Alternatives and similar repositories for axi_interconnect
Users that are interested in axi_interconnect are comparing it to the libraries listed below
Sorting:
- ☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- AXI Interconnect☆52Updated 4 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆26Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AHB Bus lite v3.0☆16Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- ☆21Updated 5 years ago
- ☆13Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Verification IP for APB protocol☆69Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- ☆36Updated 10 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 6 years ago
- 异步FIFO的内部实现☆24Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- Open-Channel Open-Way Flash Controller☆17Updated 4 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- AXI4 with a FIFO integrated with VIP☆21Updated last year
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago