Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator
☆39Jul 7, 2026Updated 2 months ago
Alternatives and similar repositories for zynqmp-hailo-ai
Users that are interested in zynqmp-hailo-ai are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆41Feb 24, 2025Updated last year
- Asynchronous FIFO for FPGAs☆12Mar 20, 2018Updated 8 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- ESnet general-purpose FPGA design library.☆14Sep 3, 2026Updated 2 weeks ago
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 7 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆39Aug 12, 2026Updated last month
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Jul 7, 2026Updated 2 months ago
- Saturn SDR Radio: Xilinx FPGA and Raspberry Pi 4 CM☆53Apr 29, 2026Updated 4 months ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 4 years ago
- UART -> AXI Bridge☆78Jul 1, 2021Updated 5 years ago
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- Object avoidance in drones using any cheap sensor☆21Jul 5, 2019Updated 7 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- LightWeight IP Application Examples for Xilinx FPGA☆16Jan 19, 2016Updated 10 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 10 months ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆18Apr 4, 2024Updated 2 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Mar 27, 2025Updated last year
- Meta Hailo☆25Aug 19, 2026Updated last month
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆17Mar 14, 2024Updated 2 years ago
- This repository holds all the projects and docs relating to our work with the Xilinx Zynq 7000 series FPGAs.☆10Apr 2, 2014Updated 12 years ago
- stepper driver for Trinamic TMC5130 and STM32 board☆11Jun 18, 2021Updated 5 years ago
- This repository shows design process for wrist watch on HDSP indicators☆13Dec 21, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆13Jun 2, 2021Updated 5 years ago
- This repository provides code for SVD and Importance sampling-based algorithms for large scale topic modeling.☆15Dec 14, 2020Updated 5 years ago
- ☆10Jun 26, 2025Updated last year
- Miscellaneous things and projects for my ZYBO and ZYNQ devices.☆11Aug 30, 2023Updated 3 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- ☆10Apr 18, 2017Updated 9 years ago
- This github contains the Vivado project, PCB schematic and control software for levitation framework at Bristol University☆17Jun 15, 2018Updated 8 years ago
- ☆36Aug 19, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆13Sep 9, 2026Updated last week
- Interacting with SAR data in standard formats in Python☆16Updated this week
- Bare metal bring-up for the Digilent Zybo board☆10Jan 26, 2017Updated 9 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- Documents and Examples about Dragino products☆10Jan 7, 2025Updated last year
- Peak sidelobe (PSL) level of binary sequences research kit. Mirror of gitlab repo: https://gitlab.com/Gluttton/PslRK .☆15Apr 15, 2023Updated 3 years ago
- LabVIEW VIP package file for the Raspberry Pi Compatible Compiler for LabVIEW☆12May 21, 2016Updated 10 years ago