fpgadeveloper / zynqmp-hailo-aiLinks
Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator
☆29Updated 9 months ago
Alternatives and similar repositories for zynqmp-hailo-ai
Users that are interested in zynqmp-hailo-ai are comparing it to the libraries listed below
Sorting:
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆71Updated 3 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆58Updated 7 months ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- MIPI CSI-2 RX☆37Updated 3 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 10 months ago
- ☆47Updated 4 years ago
- ☆28Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆65Updated 4 months ago
- ☆36Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- ☆17Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆74Updated 2 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆63Updated 3 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- PNG encoder, implemented in VHDL☆23Updated last year
- VHDL PCIe Transceiver☆30Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- 10GbE XGMII TCP/IPv4 packet generator for Verilog☆24Updated 7 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- minimal code to access ps DDR from PL☆20Updated 5 years ago
- MIPI CSI-2 + MIPI CCS Demo☆72Updated 4 years ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆71Updated 5 years ago
- ☆33Updated 2 years ago
- An CAN bus Controller implemented in Verilog☆49Updated 10 years ago