Alternatives and similar repositories for Xilinx-Unprotect:

Users that are interested in Xilinx-Unprotect are comparing it to the libraries listed below

• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆29Updated 9 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆50Updated last year
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆25Updated 6 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆88Updated 4 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆40Updated 4 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 6 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆16Updated 3 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 11 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆75Updated 10 months ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆37Updated 9 months ago
• fredrequin / verilator_gowin
  Re-coded Gowin GW1N primitives for Verilator use
  ☆14Updated 2 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆53Updated 2 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆53Updated this week
• j-marjanovic / jtag-quartus-ft232h
  ☆43Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆63Updated last month
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆37Updated 3 years ago
• AngeloJacobo / DDR3-Notes
  My notes for DDR3 SDRAM controller
  ☆28Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆33Updated 6 years ago
• tinylabs / tinylabs-cores
  Fusesoc compatible rtl cores
  ☆15Updated 2 years ago
• freecores / uart16550
  UART 16550 core
  ☆33Updated 10 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆84Updated 6 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆84Updated 11 months ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 3 years ago
• laurentiuduca / openverifla
  ☆17Updated 2 years ago