Alternatives and similar repositories for i2c:

Users that are interested in i2c are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• tomverbeure / jtag_uart_example
  Mini CPU design with JTAG UART support
  ☆19Updated 3 years ago
• tomverbeure / fpga_quick_ram_update
  Quickly update a bitstream with new RAM contents
  ☆15Updated 3 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆41Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 3 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆54Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆42Updated 4 years ago
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆18Updated last year
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• StereoNinja / StereoNinjaFPGA
  Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board
  ☆29Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆54Updated 4 months ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆41Updated last month
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆28Updated 6 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆47Updated 5 months ago
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆16Updated 4 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆25Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆86Updated 6 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago
• ZiyangYE / General-Slow-DDR3-Interface
  A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
  ☆38Updated 11 months ago