KasuganoSoraaa / simple-AXI2AHB-bridgeView external linksLinks
AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
☆42Mar 17, 2022Updated 3 years ago
Alternatives and similar repositories for simple-AXI2AHB-bridge
Users that are interested in simple-AXI2AHB-bridge are comparing it to the libraries listed below
Sorting:
- Generic AXI to AHB bridge☆18Jul 17, 2014Updated 11 years ago
- ☆11Nov 13, 2022Updated 3 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆25Nov 24, 2019Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆210Sep 2, 2025Updated 5 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- 包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）☆23Nov 7, 2022Updated 3 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 11 years ago
- ☆28Jul 9, 2025Updated 7 months ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Jan 14, 2018Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 7 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆37Oct 25, 2020Updated 5 years ago
- AMBA bus lecture material☆508Jan 21, 2020Updated 6 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- ahb scram controller, design and verification☆28Jun 20, 2018Updated 7 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆238Jul 16, 2023Updated 2 years ago
- UART -> AXI Bridge☆71Jul 1, 2021Updated 4 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year