KasuganoSoraaa / simple-AXI2AHB-bridge
AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
☆31Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for simple-AXI2AHB-bridge
- AXI Interconnect☆46Updated 3 years ago
- ☆16Updated 2 years ago
- ☆34Updated 9 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- Generic AXI to AHB bridge☆15Updated 10 years ago
- AXI总线连接器☆91Updated 4 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆20Updated 2 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- ☆9Updated 4 years ago
- Verification IP for APB protocol☆56Updated 3 years ago
- ☆21Updated 3 years ago
- ☆26Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆47Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆18Updated 4 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- UART design in SV and verification using UVM and SV☆37Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 11 years ago
- ☆34Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆24Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆16Updated 3 years ago