nimish15shah / DAG_Processor
A DAG processor and compiler for a tree-based spatial datapath.
☆13Updated 2 years ago
Alternatives and similar repositories for DAG_Processor:
Users that are interested in DAG_Processor are comparing it to the libraries listed below
- ☆26Updated last month
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last week
- ☆34Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆18Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- ☆10Updated 5 months ago
- ☆45Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆45Updated 2 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆25Updated 9 months ago
- ☆16Updated 2 years ago
- ☆15Updated 10 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆39Updated 10 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆52Updated 3 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆17Updated 8 months ago
- A general framework for optimizing DNN dataflow on systolic array☆35Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- ☆70Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆49Updated last month
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆30Updated 11 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago