Alternatives and similar repositories for iopmp-spec

Users that are interested in iopmp-spec are comparing it to the libraries listed below

• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆136Updated last week
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆45Updated 8 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆104Updated last month
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated last week
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• riscv / riscv-aia
  ☆96Updated last month
• riscv / riscv-plic-spec
  PLIC Specification
  ☆149Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆55Updated 4 years ago
• chipsalliance / tilelink
  ☆35Updated 10 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last month
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆89Updated 4 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆58Updated last week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated last month
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆113Updated this week
• riscv-software-src / riscof
  ☆92Updated last month
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆106Updated 7 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆189Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆156Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆122Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆233Updated 11 months ago