Alternatives and similar repositories for microsoft_fpga

Users that are interested in microsoft_fpga are comparing it to the libraries listed below

• wirebond / catapult_v2_pikes_peak
  Documenting Microsoft Catapult FPGA board (v2: Pikes Peak)
  ☆41Updated 5 years ago
• tow3rs / catapult-v3-smartnic-re
  Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
  ☆138Updated last year
• maswx / vu13p
  国产VU13P加速卡资料
  ☆73Updated 2 months ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆55Updated 11 months ago
• antmicro / nvme-verilog-pcie
  ☆64Updated 2 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆72Updated last year
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• sipeed / TangMega-138KPro-example
  Tang Mega 138K Pro examples
  ☆70Updated last month
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 4 years ago
• j-marjanovic / otma-pin-re
  ☆18Updated 4 years ago
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆65Updated 3 weeks ago
• TiferKing / ypcb_00338_1p1_hack
  YPCB-00338-1P1 Hack
  ☆47Updated 5 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆78Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• j-marjanovic / jtag-quartus-ft232h
  ☆46Updated 3 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆78Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆65Updated 3 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆88Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 10 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆120Updated 2 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆25Updated 8 months ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆43Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆82Updated 5 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆38Updated last year