Alternatives and similar repositories for f4pga-xc7-bram-patch

Users that are interested in f4pga-xc7-bram-patch are comparing it to the libraries listed below

• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 4 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆40Updated last week
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆46Updated 3 weeks ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆21Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated last week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆30Updated 12 years ago
• chiselverify / vhdl2verilog
  ☆18Updated 5 years ago
• nmi-leipzig / sim-x-pll
  Verilog based simulation modell for 7 Series PLL
  ☆17Updated 5 years ago
• enjoy-digital / litesata_axiom
  ☆13Updated 4 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated this week
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 3 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated 11 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• chipsalliance / fpga-interchange-schema
  ☆58Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago