FelixWinterstein / FPGA-shared-mem

Related projects: ⓘ

• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆26Updated 4 years ago
• maltanar / fpga-booleanring-bfs
  Hybrid BFS on Xilinx Zynq
  ☆18Updated 9 years ago
• austinharris / gem5-riscv
  ☆12Updated 9 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆23Updated 4 years ago
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆31Updated 3 years ago
• AWB-Tools / awb
  Architect's workbench
  ☆9Updated 8 years ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆33Updated 6 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆29Updated 2 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆32Updated 6 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆28Updated 8 years ago
• gr-rahimi / APSim
  ☆23Updated 3 years ago
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆22Updated last year
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆64Updated 6 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆41Updated 3 years ago
• CMU-SAFARI / MemBen
  Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …
  ☆19Updated 3 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆28Updated last year
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆28Updated 4 years ago
• efeslab / optimus-hypervisor
  ☆18Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• PrincetonUniversity / primesim
  A parallel and distributed simulator for thousand-core chips
  ☆22Updated 6 years ago
• LEAP-FPGA / leap-documentation
  ☆24Updated 8 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆20Updated 4 years ago
• ChenJianyunp / FPGA-Snappy-Decompressor
  A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
  ☆21Updated last year
• FelixWinterstein / LEAP-HLS
  Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework
  ☆11Updated 8 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆38Updated 4 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• fpgasystems / dma-driver
  ☆18Updated 5 years ago
• fpgasystems / Centaur
  Centaur, a framework for hybrid CPU-FPGA databases
  ☆25Updated 7 years ago