AugustinJose1221 / FFTx32Links
A 32 point radix-2 FFT module written in Verilog
☆23Updated 5 years ago
Alternatives and similar repositories for FFTx32
Users that are interested in FFTx32 are comparing it to the libraries listed below
Sorting:
- ☆22Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆27Updated 5 months ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- ☆20Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- AXI Interconnect☆54Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆26Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- APB Logic☆22Updated last month
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- ☆21Updated 5 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated 3 weeks ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆32Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- Structured UVM Course☆52Updated last year
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆73Updated 4 years ago