AugustinJose1221 / FFTx32
A 32 point radix-2 FFT module written in Verilog
☆19Updated 4 years ago
Related projects: ⓘ
- AXI Interconnect☆44Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆32Updated 2 years ago
- UART -> AXI Bridge☆52Updated 3 years ago
- ☆14Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆12Updated 2 months ago
- 异步FIFO的内部实现☆23Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆33Updated 9 months ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆38Updated 5 years ago
- ☆19Updated 4 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- ☆11Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- R22SDF FFT VLSI/FPGA investigate and implementation☆12Updated 2 years ago
- ☆32Updated 9 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆28Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆27Updated 5 years ago
- ☆20Updated 3 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆12Updated 9 years ago
- verification of simple axi-based cache☆16Updated 5 years ago
- ☆19Updated this week
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆40Updated 4 months ago
- ☆31Updated 2 years ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆51Updated last month
- 学习AXI接口,以及xilinx DDR3 IP使用☆34Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- To design test bench of the APB protocol☆16Updated 3 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆11Updated 2 years ago
- DMA core compatible with AHB3-Lite☆9Updated 5 years ago
- AHB DMA 32 / 64 bits☆48Updated 10 years ago