AugustinJose1221 / FFTx32Links
A 32 point radix-2 FFT module written in Verilog
☆23Updated 5 years ago
Alternatives and similar repositories for FFTx32
Users that are interested in FFTx32 are comparing it to the libraries listed below
Sorting:
- ☆25Updated 3 months ago
- ☆21Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Implementation of the PCIe physical layer☆50Updated 3 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48Updated last year
- ☆20Updated 2 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆24Updated last week
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- AXI Interconnect☆53Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- APB Logic☆20Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- ☆26Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Verilog RTL Design☆45Updated 4 years ago
- AHB Bus lite v3.0☆16Updated 6 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- ☆13Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago