Alternatives and similar repositories for BRISKI:

Users that are interested in BRISKI are comparing it to the libraries listed below

• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆62Updated 11 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆33Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆26Updated 2 weeks ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆46Updated 11 months ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last month
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• SymbiFlow / nextpnr
  nextpnr portable FPGA place and route tool
  ☆20Updated 8 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 5 months ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated last year
• sjohann81 / hf-risc
  HF-RISC SoC
  ☆32Updated 2 weeks ago
• dovebutch / tlv-comp
  ☆27Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆55Updated 6 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆32Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated last month
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago