Alternatives and similar repositories for BRISKI

Users that are interested in BRISKI are comparing it to the libraries listed below

• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆49Updated last month
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆98Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated last week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆81Updated 5 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 4 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆47Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 6 months ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated last week
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 8 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆63Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• pieter3d / simview
  ☆79Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• FPGA-House-AG / BrightAI-Blackwire
  BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
  ☆48Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 9 months ago
• efabless / clear
  ☆70Updated 11 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• pulp-platform / svase
  ☆32Updated 6 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆49Updated 2 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated this week
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆58Updated this week