BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.
☆32Aug 9, 2026Updated 3 weeks ago
Alternatives and similar repositories for BRISKI
Users that are interested in BRISKI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- HeiChips 2025 LibreLane Workshop☆18Aug 25, 2025Updated last year
- ☆22Dec 27, 2024Updated last year
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆20Jul 25, 2023Updated 3 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Jun 8, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Mar 27, 2024Updated 2 years ago
- HeiChips 2025 Tapeout on IHP SG13G2 130nm process☆23Apr 10, 2026Updated 4 months ago
- ☆13Jun 23, 2026Updated 2 months ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆24Nov 17, 2021Updated 4 years ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆228Feb 19, 2026Updated 6 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Aug 31, 2026Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Post-Silicon Validation Tool based on REVERSI☆12Dec 10, 2025Updated 8 months ago
- A Barrel design of RV32I☆22Jul 30, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Open source designs developed with the IHP 130nm BiCMOS Open PDK in the FMD_QNC project. Documentation at https://ihp-open-designlib.read…☆75Jun 5, 2026Updated 3 months ago
- Handle Fast Signal Traces (fst) in Python☆16Jun 11, 2025Updated last year
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆62Updated this week
- Menu bar app to quickly hide or display your desktop files☆12Jan 2, 2023Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆122Jun 18, 2026Updated 2 months ago
- RISC-V Processor written in Amaranth HDL☆40Jan 21, 2022Updated 4 years ago
- RISC-V out-of-order core for education and research purposes☆95Updated this week
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Jul 23, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Full Speed USB DFU interface for FPGA and ASIC designs☆21Mar 10, 2024Updated 2 years ago
- ☆17Oct 1, 2024Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆77Apr 2, 2019Updated 7 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated 2 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 6 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- 3D FPGA Architecture Exploration Tool☆22Jun 22, 2026Updated 2 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆151Aug 26, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Cycle accurate MC6502 compatible processor in Verilog.☆16Oct 11, 2021Updated 4 years ago
- GDB server to debug CPU simulation waveform traces☆44Feb 21, 2022Updated 4 years ago
- ☆20Apr 8, 2026Updated 5 months ago
- Multi-Dataflow Composer (MDC) design suite☆11Aug 3, 2026Updated last month
- An (incomplete) Common Lisp implementation of the iCalendar RFC5545 specification.☆14Apr 19, 2019Updated 7 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆62Oct 27, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year