rooinasuit / AXI_to_SPILinks
Designing means to communicate as an SPI master, being a part of AXI interface
☆17Updated last year
Alternatives and similar repositories for AXI_to_SPI
Users that are interested in AXI_to_SPI are comparing it to the libraries listed below
Sorting:
- AXI Interconnect☆50Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- ☆20Updated 2 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Verification IP for APB protocol☆66Updated 4 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆55Updated 8 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆46Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆52Updated 4 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- ☆36Updated 9 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Verification IP for I2C protocol☆46Updated 3 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- AMBA 3 AHB UVM TB☆32Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆33Updated 5 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- ☆33Updated last month
- SystemVerilog UVM testbench example☆33Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Updated 5 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year