rooinasuit / AXI_to_SPILinks
Designing means to communicate as an SPI master, being a part of AXI interface
☆17Updated 2 years ago
Alternatives and similar repositories for AXI_to_SPI
Users that are interested in AXI_to_SPI are comparing it to the libraries listed below
Sorting:
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- ☆20Updated 2 years ago
- Verification IP for APB protocol☆71Updated 4 years ago
- Implementation of the PCIe physical layer☆50Updated 3 months ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- UART -> AXI Bridge☆63Updated 4 years ago
- SystemVerilog examples and projects☆19Updated 4 months ago
- AXI Interconnect☆53Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆41Updated 3 years ago
- ☆49Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- SystemVerilog UVM testbench example☆35Updated last year
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆27Updated 8 months ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆55Updated 5 years ago
- Examples and reference for System Verilog Assertions☆88Updated 8 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- AMBA 3 AHB UVM TB☆33Updated 6 years ago
- This is the repository for the IEEE version of the book☆74Updated 5 years ago
- Structured UVM Course☆51Updated last year
- UVM Testbench For SystemVerilog Combinator Implementation☆56Updated 8 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago