Yu-Maryland / Differentiable_Scheduler_ICML24Links
Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
☆21Updated 7 months ago
Alternatives and similar repositories for Differentiable_Scheduler_ICML24
Users that are interested in Differentiable_Scheduler_ICML24 are comparing it to the libraries listed below
Sorting:
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 9 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Open-source RTL logic simulator with CUDA acceleration☆19Updated last week
- ☆16Updated 3 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 4 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ☆12Updated 6 months ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization☆30Updated 6 months ago
- A unified programming framework for high and portable performance across FPGAs and GPUs☆11Updated 2 months ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆19Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 4 months ago
- EQueue Dialect☆40Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆32Updated 10 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆13Updated last month
- DATuner Repository☆18Updated 6 years ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆13Updated 4 years ago
- ☆18Updated last month
- Control Logic Synthesis: Drawing the Rest of the OWL☆11Updated 11 months ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- This is a python repo for flattening Verilog☆16Updated 3 weeks ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆12Updated 2 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 6 months ago
- This is a repo to store circuit design datasets☆17Updated last year
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆24Updated 4 years ago
- ☆10Updated 2 years ago
- ☆16Updated 4 years ago