marcelwa / aigverseLinks
A Python library for working with logic networks, synthesis, and optimization.
☆65Updated this week
Alternatives and similar repositories for aigverse
Users that are interested in aigverse are comparing it to the libraries listed below
Sorting:
- An open-source design automation framework for Field-coupled Nanotechnologies☆78Updated this week
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆21Updated 4 months ago
- Showcase examples for EPFL logic synthesis libraries☆195Updated last year
- ☆26Updated 4 years ago
- C++ header-only exact synthesis library☆18Updated 2 years ago
- A logic synthesis tool☆78Updated last month
- ASIC Design kit for Skywater 130 for use with mflowgen☆13Updated 2 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆16Updated 3 months ago
- ☆17Updated 4 years ago
- An advanced header-only exact synthesis library☆27Updated 2 years ago
- State-of-the-art in reversible logic synthesis☆22Updated 9 years ago
- A circuit toolkit☆105Updated 5 years ago
- Research paper based on or related to ABC.☆51Updated last month
- A design automation framework to engineer decision diagrams yourself☆21Updated last week
- SyReC Synthesizer - A Tool for HDL-based Synthesis of Reversible Circuits☆31Updated this week
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- ☆22Updated 2 months ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆37Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆55Updated 7 months ago
- C++ truth table library☆59Updated last month
- IDEA project source files☆108Updated 2 weeks ago
- GPU-based logic synthesis tool☆90Updated 3 weeks ago
- Problems and Results of IWLS 2022 Programming Contest☆18Updated 4 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆35Updated last year
- C++ logic network library☆247Updated 3 weeks ago
- ☆18Updated 9 months ago
- ☆24Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago