marcelwa / aigverseLinks
A Python library for working with logic networks, synthesis, and optimization.
☆71Updated last week
Alternatives and similar repositories for aigverse
Users that are interested in aigverse are comparing it to the libraries listed below
Sorting:
- An open-source design automation framework for Field-coupled Nanotechnologies☆85Updated this week
- State-of-the-art in reversible logic synthesis☆24Updated 9 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 10 months ago
- Showcase examples for EPFL logic synthesis libraries☆202Updated last year
- ☆28Updated 5 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆22Updated 8 months ago
- A design automation framework to engineer decision diagrams yourself☆25Updated last week
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Updated 5 years ago
- Problems and Results of IWLS 2022 Programming Contest☆21Updated 9 months ago
- A logic synthesis tool☆84Updated 5 months ago
- SyReC Synthesizer - A Tool for HDL-based Synthesis of Reversible Circuits☆37Updated this week
- C++ header-only exact synthesis library☆17Updated 3 years ago
- A circuit toolkit☆107Updated 5 years ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- Research paper based on or related to ABC.☆70Updated 3 weeks ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Updated last year
- Awesome machine learning for logic synthesis☆30Updated 3 years ago
- ☆19Updated 5 years ago
- ☆24Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆56Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- ☆16Updated 4 months ago
- GPU-based logic synthesis tool☆97Updated 2 months ago
- ☆30Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆30Updated 6 years ago
- ☆27Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- IDEA project source files☆111Updated 3 months ago